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219 条记录 (耗时 0.033 秒)

    Circuit for operating a control transistor from a fusible link
    1.
    发明授权
    Circuit for operating a control transistor from a fusible link 失效
    用于从可熔链路操作控制晶体管的电路

    公开(公告)号：US5999037A

    公开(公告)日：1999-12-07

    申请号：US904397

    申请日：1997-07-31

    申请人： Kerry Bernstein ,  Daniel C. Edelstein ,  William A. Klaasen ,  Wilbur D. Pricer

    发明人： Kerry Bernstein ,  Daniel C. Edelstein ,  William A. Klaasen ,  Wilbur D. Pricer

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/785

    摘要： A circuit for enabling a controlled transistor in response to an ablated fusible link. The fusible link is configured so that no d.c. potential resides on the link once it has been ablated. A source of alternating voltage is capacitively coupled to the fusible link and maintains the fusible link from reconnection due to dendrite formation once it is ablated. An a.c. to d.c. voltage converter is used to signal the change in condition of the fusible link, thus, actuating a control transistor of a redundant circuit element in a replacement operation.

    摘要翻译： 一种用于响应于消融的可熔链路启用受控晶体管的电路。 熔丝链接被配置为没有直流 一旦消融，电位就位于链接上。 交流电压源电容耦合到可熔链路，并且一旦烧蚀就会由于枝晶形成而使可熔连接件重新连接。 一个 到达 电压转换器用于发信号通知熔断条件的变化，从而在更换操作中致动冗余电路元件的控制晶体管。

    Tungsten metallization: structure and fabrication of same
    7.
    发明授权
    Tungsten metallization: structure and fabrication of same 失效
    钨金属化：其结构和制造相同

    公开(公告)号：US08564132B2

    公开(公告)日：2013-10-22

    申请号：US13211722

    申请日：2011-08-17

    申请人： Chih-Chao Yang ,  Daniel C. Edelstein

    发明人： Chih-Chao Yang ,  Daniel C. Edelstein

    IPC分类号： H01L23/482

    CPC分类号： H01L21/76838 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76895

    摘要： A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

    摘要翻译： 提供局部互连结构，其中形成在中间线（MOL）电介质材料内的钨区域，即钨柱，在多重互连图案化工艺期间不被损坏和/或污染。 这在本公开内容中通过在顶部表面内形成自对准的氮化钨钝化层，并且在钨区域的上侧壁部分之上延伸到包括形成在其中的第一互连图案的MOL介电材料之上。 在自对准氮化钨钝化层的形成过程中，还会在MOL介电材料的暴露表面内形成富含氮的电介质表面。 然后形成与第一互连图案相邻但不连接的第二布线图案。 由于在钨区域上存在自对准的氮化钨钝化层，不会发生钨区域的破坏和/或污染。

    Noble metal cap for interconnect structures
    8.
    发明授权
    Noble metal cap for interconnect structures 有权
    用于互连结构的贵金属盖

    公开(公告)号：US08497580B2

    公开(公告)日：2013-07-30

    申请号：US13191090

    申请日：2011-07-26

    申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Fenton R. McFeely

    发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Fenton R. McFeely

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L21/76826 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.

    摘要翻译： 提供了包括具有约3.0或更小介电常数的介电材料的互连结构。 该低k电介质材料具有至少一个具有嵌入其中的上表面的导电材料。 电介质材料还具有在形成贵金属盖之前被制成疏水性的表面层。 贵金属盖直接位于至少一个导电材料的上表面上。 由于在电介质材料上存在疏水表面层，贵金属盖基本上不会延伸到与至少一种导电材料相邻的电介质材料的疏水表面层上，并且没有贵金属帽的金属残留物 沉积形式在该疏水电介质表面上。

    Barrier layer formation for metal interconnects through enhanced impurity diffusion
    9.
    发明授权
    Barrier layer formation for metal interconnects through enhanced impurity diffusion 有权
    金属互连的阻挡层形成通过增强的杂质扩散

    公开(公告)号：US08492289B2

    公开(公告)日：2013-07-23

    申请号：US12882500

    申请日：2010-09-15

    申请人： Daniel C. Edelstein ,  Takeshi Nogami ,  Hosadurga K. Shobha

    发明人： Daniel C. Edelstein ,  Takeshi Nogami ,  Hosadurga K. Shobha

    IPC分类号： H01L21/31

    CPC分类号： H01L23/53238 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a barrier layer for metal interconnects of an integrated circuit device includes forming a first cap layer over a top surface of a conductive line of the integrated circuit device in a manner that facilitates a controllable dose of oxygen provided to the top surface of the conductive line, the conductive line comprising a metal formed over a seed layer that is an impurity alloy of the metal; and annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with the controllable dose of oxygen, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line.

    摘要翻译： 形成用于集成电路器件的金属互连的势垒层的方法包括在集成电路器件的导电线的顶表面之上形成第一帽层，以便于提供给顶部表面的氧的可控剂量 所述导电线包括在作为所述金属的杂质合金的种子层上形成的金属; 以及对所述集成电路器件进行退火以将所述种子层的扩散杂质原子与可控量的氧组合，从而在所述第一覆盖层和所述导电线的顶表面之间的界面处形成杂质氧化物层。