公开(公告)号：US20140061915A1

公开(公告)日：2014-03-06

申请号：US13599295

申请日：2012-08-30

申请人： Christopher N. Collins ,  Daniel C. Edelstein ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Andrew H. Simon ,  Richard P. Volant

发明人： Christopher N. Collins ,  Daniel C. Edelstein ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Andrew H. Simon ,  Richard P. Volant

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/76873 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/32145 ,  H01L2224/8001 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A method of forming an integrated circuit device includes forming a diffusion barrier layer in an opening defined in a substrate; forming a highly doped copper alloy seed layer over the diffusion barrier layer, the copper alloy seed layer having a minority alloy component having a concentration greater than 0.5% atomic; and forming a copper layer over the copper alloy seed layer so as to define a wiring structure of the integrated circuit device.

摘要翻译： 形成集成电路器件的方法包括在限定在衬底中的开口中形成扩散阻挡层; 在所述扩散阻挡层上形成高掺杂的铜合金种子层，所述铜合金种子层具有浓度大于0.5％原子的少数合金成分; 以及在所述铜合金晶种层上形成铜层，以限定所述集成电路器件的布线结构。

公开(公告)号：US20120175789A1

公开(公告)日：2012-07-12

申请号：US12987202

申请日：2011-01-10

申请人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  Robert Hannon ,  Emily R. Kinser ,  William F. Landers ,  Kevin S. Patrarca ,  Richard P. Volant ,  Kevin R. Winstel

发明人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  Robert Hannon ,  Emily R. Kinser ,  William F. Landers ,  Kevin S. Patrarca ,  Richard P. Volant ,  Kevin R. Winstel

IPC分类号： H01L23/544 ,  H01L21/02

CPC分类号： H01L21/76898 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8385 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2224/83

摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

摘要翻译： 公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。 该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。

公开(公告)号：US08546961B2

公开(公告)日：2013-10-01

申请号：US12987202

申请日：2011-01-10

申请人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  Robert Hannon ,  Emily R. Kinser ,  William F. Landers ,  Kevin S. Petrarca ,  Richard P. Volant ,  Kevin R. Winstel

发明人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  Robert Hannon ,  Emily R. Kinser ,  William F. Landers ,  Kevin S. Petrarca ,  Richard P. Volant ,  Kevin R. Winstel

IPC分类号： H01L23/544 ,  H01L21/02

CPC分类号： H01L21/76898 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8385 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2224/83

摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

摘要翻译： 公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。 该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。

公开(公告)号：US08691691B2

公开(公告)日：2014-04-08

申请号：US13194214

申请日：2011-07-29

申请人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  William F. Landers ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  William F. Landers ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L21/44 ,  H01L21/311

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11602 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/11616 ,  H01L2224/13009 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13583 ,  H01L2224/13584 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13683 ,  H01L2224/13684 ,  H01L2224/13687 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/053 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/00

摘要： The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.

摘要翻译： 本发明包括用于构建具有可用作互连结构的TSV柱的芯片的处理方法和结果的结构的实施例。 该过程包括在TSV和衬底之间沉积TSV和衬底之间的双重扩散阻挡层。 TSV然后从衬底的背面露出，使得TSV的至少一部分从衬底突出，并且可以用作用于将芯片连接到另一表面的接触件。 所产生的TSV是刚性的，高导电性的，可以放置在紧密连接的接触网格中，并减少CTE失配的影响。

公开(公告)号：US20130026606A1

公开(公告)日：2013-01-31

申请号：US13194214

申请日：2011-07-29

申请人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  William F. Landers ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  William F. Landers ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L23/522 ,  H01L21/98 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11602 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/11616 ,  H01L2224/13009 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13583 ,  H01L2224/13584 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13683 ,  H01L2224/13684 ,  H01L2224/13687 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/053 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/00

摘要： The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.

摘要翻译： 本发明包括用于构建具有可用作互连结构的TSV柱的芯片的处理方法和结果的结构的实施例。 该过程包括在TSV和衬底之间沉积TSV和衬底之间的双重扩散阻挡层。 TSV然后从衬底的背面露出，使得TSV的至少一部分从衬底突出，并且可以用作用于将芯片连接到另一表面的接触件。 所产生的TSV是刚性的，高导电性的，可以放置在紧密连接的接触网格中，并减少CTE失配的影响。

公开(公告)号：US08633580B2

公开(公告)日：2014-01-21

申请号：US13569231

申请日：2012-08-08

申请人： Richard P. Volant ,  Mukta G. Farooq ,  Kevin S. Petrarca

发明人： Richard P. Volant ,  Mukta G. Farooq ,  Kevin S. Petrarca

IPC分类号： H01L25/11

CPC分类号： H01L21/76879 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/29 ,  H01L24/82 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/29 ,  H01L2224/29298 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/05552 ,  H01L2924/00

摘要： A microelectronic assembly having a through hole extending through a first wafer (or chip) and a second wafer (or chip) are provided. The first and second wafers (or chips) have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers (or chips) leaving a gap between the confronting faces. A hole is etched in the first wafer (or chip), then material is sputtered to form a wall of material in the gap between wafers (or chips). Etching continues to extend the hole into or through the second wafer (or chip). The hole is filled to form a substantially vertical through silicon conductive via.

摘要翻译： 提供具有延伸穿过第一晶片（或芯片）和第二晶片（或芯片）的通孔的微电子组件。 第一和第二晶片（或芯片）在面处具有面对面和金属特征，所述表面和金属特征被连接在一起以组装在相对面之间留下间隙的第一和第二晶片（或芯片）。 在第一晶片（或芯片）中蚀刻孔，然后溅射材料以在晶片（或芯片）之间的间隙中形成材料壁。 蚀刻继续将孔扩展到第二晶片（或芯片）中或通过第二晶片（或芯片）。 该孔被填充以形成基本垂直的通过硅的导电通孔。

公开(公告)号：US08492878B2

公开(公告)日：2013-07-23

申请号：US12840688

申请日：2010-07-21

申请人： Mukta G. Farooq ,  Robert Hannon ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Robert Hannon ,  Richard P. Volant

IPC分类号： H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81801 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

摘要： A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination.

摘要翻译： 提供了由于背面平坦化处理而对金属污染免疫的贯穿衬底通孔（TSV）结构。 在形成贯穿衬底通孔（TSV）沟槽之后，扩散阻挡衬里共形沉积在TSV沟槽的侧壁上。 通过在扩散阻挡衬里的垂直部分上沉积介电材料形成电介质衬垫。 通过随后填充TSV沟槽形成金属导电通孔结构。 去除扩散阻挡衬里的水平部分。 扩散阻挡衬里通过阻挡源自金属导电通路结构的残余金属材料进入衬底的半导体材料来保护衬底的半导体材料，从而保护衬底内的半导体器件免受金属污染。

公开(公告)号：US20110095435A1

公开(公告)日：2011-04-28

申请号：US12607098

申请日：2009-10-28

申请人： Richard P. Volant ,  Mukta G. Farooq ,  Paul F. Findeis ,  Kevin S. Petrarca

发明人： Richard P. Volant ,  Mukta G. Farooq ,  Paul F. Findeis ,  Kevin S. Petrarca

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.

摘要翻译： 硅通孔（TSV）结构在硅衬底内形成独特的同轴或三轴互连。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。 还描述了制造这种TSV结构的方法。

公开(公告)号：US07816248B2

公开(公告)日：2010-10-19

申请号：US12138482

申请日：2008-06-13

申请人： Mukta G. Farooq ,  Lacrtis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Lacrtis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05085 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

摘要翻译： 公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附 导电衬里进入焊接接头结构。 该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。 衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。

公开(公告)号：US20080248643A1

公开(公告)日：2008-10-09

申请号：US12138482

申请日：2008-06-13

申请人： Mukta G. Farooq ,  Laertis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Laertis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05085 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

摘要翻译： 公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附 导电衬里进入焊接接头结构。 该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。 衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。