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1.发明授权Methods of forming semiconductor devices having self aligned semiconductor mesas and contact layers 有权形成具有自对准半导体台面和接触层的半导体器件的方法公开(公告)号：US07160747B2
公开(公告)日：2007-01-09
申请号：US10741705
申请日：2003-12-19
IPC分类号： H01L21/00
CPC分类号： H01L33/145 , H01S5/021 , H01S5/0421 , H01S5/0425 , H01S5/22 , H01S5/2205 , H01S5/2206 , H01S5/2214 , H01S5/2231 , H01S5/2275 , H01S5/32341 , H01S2301/176
摘要： Methods of forming a semiconductor device can include forming a semiconductor structure on a substrate, the semiconductor structure having mesa sidewalls and a mesa surface opposite the substrate. A contact layer can be formed on the mesa surface wherein the contact layer has sidewalls and a contact surface opposite the mesa surface and wherein the contact layer extends across substantially an entirety of the mesa surface. A passivation layer can be formed on the mesa sidewalls and on portions of the contact layer sidewalls adjacent the mesa surface, and the passivation layer can expose substantially an entirety of the contact surface of the contact layer.
摘要翻译： 形成半导体器件的方法可以包括在衬底上形成半导体结构，半导体结构具有台面侧壁和与衬底相对的台面。 接触层可以形成在台面表面上，其中接触层具有侧壁和与台面表面相对的接触表面，并且其中接触层延伸穿过基本上整个台面表面。 可以在台面侧壁和邻近台面表面的接触层侧壁的部分上形成钝化层，并且钝化层可以暴露接触层的基本上整个接触表面。
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2.发明授权Semiconductor devices having self aligned semiconductor mesas and contact layers 有权具有自对准半导体台面和接触层的半导体器件公开(公告)号：US07613219B2
公开(公告)日：2009-11-03
申请号：US11520383
申请日：2006-09-13
CPC分类号： H01L33/145 , H01S5/021 , H01S5/0421 , H01S5/0425 , H01S5/22 , H01S5/2205 , H01S5/2206 , H01S5/2214 , H01S5/2231 , H01S5/2275 , H01S5/32341 , H01S2301/176
摘要： Methods of forming a semiconductor device can include forming a semiconductor structure on a substrate, the semiconductor structure having mesa sidewalls and a mesa surface opposite the substrate. A contact layer can be formed on the mesa surface wherein the contact layer has sidewalls and a contact surface opposite the mesa surface and wherein the contact layer extends across substantially an entirety of the mesa surface. A passivation layer can be formed on the mesa sidewalls and on portions of the contact layer sidewalls adjacent the mesa surface, and the passivation layer can expose substantially an entirety of the contact surface of the contact layer. Related devices are also discussed.
摘要翻译： 形成半导体器件的方法可以包括在衬底上形成半导体结构，半导体结构具有台面侧壁和与衬底相对的台面。 接触层可以形成在台面表面上，其中接触层具有侧壁和与台面表面相对的接触表面，并且其中接触层延伸穿过基本上整个台面表面。 可以在台面侧壁和邻近台面表面的接触层侧壁的部分上形成钝化层，并且钝化层可以暴露接触层的基本上整个接触表面。 还讨论了相关设备。
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3.发明申请SEMICONDUCTOR DEVICES INCLUDING MESA STRUCTURES AND MULTIPLE PASSIVATION LAYERS 有权包括MESA结构和多个钝化层的半导体器件公开(公告)号：US20080135982A1
公开(公告)日：2008-06-12
申请号：US11959725
申请日：2007-12-19
IPC分类号： H01L29/06
CPC分类号： H01L33/145 , H01S5/021 , H01S5/0421 , H01S5/0425 , H01S5/22 , H01S5/2205 , H01S5/2206 , H01S5/2214 , H01S5/2231 , H01S5/2275 , H01S5/32341 , H01S2301/176
摘要： A semiconductor device including a semiconductor structure defining a mesa having a mesa surface and mesa sidewalls, and first and second passivation layers. The first passivation layer may be on at least portions of the mesa sidewalls, at least a portion of the mesa surface may be free of the first passivation layer, and the first passivation layer may include a first material. The second passivation layer may be on the first passivation layer, at least a portion of the mesa surface may be free of the second passivation layer, and the second passivation layer may include a second material different than the first material.
摘要翻译： 一种半导体器件，包括限定具有台面表面和台面侧壁的台面的半导体结构以及第一和第二钝化层。 第一钝化层可以在台面侧壁的至少部分上，台面表面的至少一部分可以没有第一钝化层，并且第一钝化层可以包括第一材料。 第二钝化层可以在第一钝化层上，台面表面的至少一部分可以没有第二钝化层，并且第二钝化层可以包括不同于第一材料的第二材料。
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4.发明授权Semiconductor devices including mesa structures and multiple passivation layers 有权半导体器件包括台面结构和多个钝化层公开(公告)号：US07642626B2
公开(公告)日：2010-01-05
申请号：US11959725
申请日：2007-12-19
IPC分类号： H01L29/06 , H01L33/00 , H01L29/74 , H01L31/111
CPC分类号： H01L33/145 , H01S5/021 , H01S5/0421 , H01S5/0425 , H01S5/22 , H01S5/2205 , H01S5/2206 , H01S5/2214 , H01S5/2231 , H01S5/2275 , H01S5/32341 , H01S2301/176
摘要： A semiconductor device including a semiconductor structure defining a mesa having a mesa surface and mesa sidewalls, and first and second passivation layers. The first passivation layer may be on at least portions of the mesa sidewalls, at least a portion of the mesa surface may be free of the first passivation layer, and the first passivation layer may include a first material. The second passivation layer may be on the first passivation layer, at least a portion of the mesa surface may be free of the second passivation layer, and the second passivation layer may include a second material different than the first material.
摘要翻译： 一种半导体器件，包括限定具有台面表面和台面侧壁的台面的半导体结构以及第一和第二钝化层。 第一钝化层可以在台面侧壁的至少部分上，台面表面的至少一部分可以没有第一钝化层，并且第一钝化层可以包括第一材料。 第二钝化层可以在第一钝化层上，台面表面的至少一部分可以没有第二钝化层，并且第二钝化层可以包括不同于第一材料的第二材料。
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5.发明授权Methods of forming semiconductor devices including mesa structures and multiple passivation layers 有权形成半导体器件的方法包括台面结构和多个钝化层公开(公告)号：US07329569B2
公开(公告)日：2008-02-12
申请号：US10741240
申请日：2003-12-19
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8242 , H01L21/8236
CPC分类号： H01L33/145 , H01S5/021 , H01S5/0421 , H01S5/0425 , H01S5/22 , H01S5/2205 , H01S5/2206 , H01S5/2214 , H01S5/2231 , H01S5/2275 , H01S5/32341 , H01S2301/176
摘要： A method of forming a semiconductor device may include forming a semiconductor structure on a substrate wherein the semiconductor structure defines a mesa having a mesa surface opposite the substrate and mesa sidewalls between the mesa surface and the substrate. A first passivation layer can be formed on at least portions of the mesa sidewalls and on the substrate adjacent the mesa sidewalls wherein at least a portion of the mesa surface is free of the first passivation layer and wherein the first passivation layer comprises a first material. A second passivation layer can be formed on the first passivation layer wherein at least a portion of the mesa surface is free of the second passivation layer, and wherein the second passivation layer comprises a second material different than the first material. Related devices are also discussed.
摘要翻译： 形成半导体器件的方法可以包括在衬底上形成半导体结构，其中半导体结构限定具有与衬底相对的台面的台面和台面与衬底之间的台面侧壁。 第一钝化层可以形成在台面侧壁的至少部分和邻近台面侧壁的基板上，其中台面表面的至少一部分不含第一钝化层，并且其中第一钝化层包括第一材料。 可以在第一钝化层上形成第二钝化层，其中台面表面的至少一部分不含第二钝化层，并且其中第二钝化层包括不同于第一材料的第二材料。 还讨论了相关设备。
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公开(公告)号：US06803602B2
公开(公告)日：2004-10-12
申请号：US10427984
申请日：2003-05-02
IPC分类号： H01L310256
CPC分类号： H01L21/0237 , H01L21/02378 , H01L21/02458 , H01L21/02491 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L21/02647 , H01L21/0265 , H01S5/3202 , H01S2304/12
摘要： A method of fabricating a gallium nitride-based semiconductor structure on a substrate includes the steps of forming a mask having at least one opening therein directly on the substrate, growing a buffer layer through the opening, and growing a layer of gallium nitride upwardly from the buffer layer and laterally across the mask. During growth of the gallium nitride from the mask, the vertical and horizontal growth rates of the gallium nitride layer are maintained at rates sufficient to prevent polycrystalline material nucleating on said mask from interrupting the lateral growth of the gallium nitride layer. In an alternative embodiment, the method includes forming at least one raised portion defining adjacent trenches in the substrate and forming a mask on the substrate, the mask having at least one opening over the upper surface of the raised portion. A buffer layer may be grown from the upper surface of the raised portion. The gallium nitride layer is then grown laterally by pendeoepitaxy over the trenches.
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7.发明授权Single step pendeo- and lateral epitaxial overgrowth of group III-nitride epitaxial layers with group III-nitride buffer layer and resulting structures 有权具有III族氮化物缓冲层和所得结构的III族氮化物外延层的单步侧向和横向外延过度生长公开(公告)号：US06764932B2
公开(公告)日：2004-07-20
申请号：US10056607
申请日：2002-01-24
IPC分类号： H01L213205
CPC分类号： H01L21/0237 , H01L21/02378 , H01L21/02458 , H01L21/02491 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L21/02647 , H01L21/0265 , H01S5/3202 , H01S2304/12
摘要： A method of fabricating a gallium nitride-based semiconductor structure on a substrate includes the steps of forming a mask having at least one opening therein directly on the substrate, growing a buffer layer through the opening, and growing a layer of gallium nitride upwardly from the buffer layer and laterally across the mask. During growth of the gallium nitride from the mask, the vertical and horizontal growth rates of the gallium nitride layer are maintained at rates sufficient to prevent polycrystalline material nucleating on said mask from interrupting the lateral growth of the gallium nitride layer. In an alternative embodiment, the method includes forming at least one raised portion defining adjacent trenches in the substrate and forming a mask on the substrate, the mask having at least one opening over the upper surface of the raised portion. A buffer layer may be grown from the upper surface of the raised portion. The gallium nitride layer is then grown laterally by pendeoepitaxy over the trenches.
摘要翻译： 在衬底上制造氮化镓基半导体结构的方法包括以下步骤：在衬底上直接形成具有至少一个开口的掩模，通过该开口生长缓冲层，并从其中向上生长一层氮化镓 缓冲层和横向穿过掩模。 在从掩模生长氮化镓期间，氮化镓层的垂直和水平生长速率保持在足以防止在所述掩模上成核的多晶材料中断氮化镓层的横向生长的速率。 在替代实施例中，该方法包括形成限定衬底中相邻沟槽的至少一个凸起部分，并在衬底上形成掩模，该掩模在凸起部分的上表面上具有至少一个开口。 缓冲层可以从凸起部分的上表面生长。 然后氮化镓层通过在沟槽上的外延生长而横向生长。
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8.发明授权Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures 有权具有III族氮化物缓冲层和所得结构的III族氮化物外延层的单步横向和横向外延过度生长公开(公告)号：US06812053B1
公开(公告)日：2004-11-02
申请号：US09679799
申请日：2000-10-05
IPC分类号： H01L2100
CPC分类号： H01L21/0237 , H01L21/02378 , H01L21/02458 , H01L21/02491 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L21/02647 , H01L21/0265 , H01S5/3202 , H01S2304/12
摘要： A method of fabricating a gallium nitride-based semiconductor structure on a substrate includes the steps of forming a mask having at least one opening therein directly on the substrate, growing a buffer layer through the opening, and growing a layer of gallium nitride upwardly from the buffer layer and laterally across the mask. During growth of the gallium nitride from the mask, the vertical and horizontal growth rates of the gallium nitride layer are maintained at rates sufficient to prevent polycrystalline material nucleating on said mask from interrupting the lateral growth of the gallium nitride layer. In an alternative embodiment, the method includes forming at least one raised portion defining adjacent trenches in the substrate and forming a mask on the substrate, the mask having at least one opening over the upper surface of the raised portion. A buffer layer may be grown from the upper surface of the raised portion. The gallium nitride layer is then grown laterally by pendeoepitaxy over the trenches.
摘要翻译： 在衬底上制造氮化镓基半导体结构的方法包括以下步骤：在衬底上直接形成具有至少一个开口的掩模，通过该开口生长缓冲层，并从其中向上生长一层氮化镓 缓冲层和横向穿过掩模。 在从掩模生长氮化镓期间，氮化镓层的垂直和水平生长速率保持在足以防止在所述掩模上成核的多晶材料中断氮化镓层的横向生长的速率。 在替代实施例中，该方法包括形成限定衬底中相邻沟槽的至少一个凸起部分，并在衬底上形成掩模，该掩模在凸起部分的上表面上具有至少一个开口。 缓冲层可以从凸起部分的上表面生长。 然后氮化镓层通过在沟槽上的外延生长而横向生长。
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公开(公告)号：US06582986B2
公开(公告)日：2003-06-24
申请号：US09934270
申请日：2001-08-21
IPC分类号： H01L2100
CPC分类号： H01L21/0237 , H01L21/02378 , H01L21/02458 , H01L21/02491 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L21/02647 , H01L21/0265 , H01S5/3202 , H01S2304/12
摘要： A method of fabricating a gallium nitride-based semiconductor structure on a substrate includes the steps of forming a mask having at least one opening therein directly on the substrate, growing a buffer layer through the opening, and growing a layer of gallium nitride upwardly from the buffer layer and laterally across the mask. During growth of the gallium nitride from the mask, the vertical and horizontal growth rates of the gallium nitride layer are maintained at rates sufficient to prevent polycrystalline material nucleating on said mask from interrupting the lateral growth of the gallium nitride layer. In an alternative embodiment, the method includes forming at least one raised portion defining adjacent trenches in the substrate and forming a mask on the substrate, the mask having at least one opening over the upper surface of the raised portion. A buffer layer may be grown from the upper surface of the raised portion. The gallium nitride layer is then grown laterally by pendeoepitaxy over the trenches.
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10.发明授权Semiconductor devices having low threading dislocations and improved light extraction and methods of making the same 有权具有低穿透位错和改进的光提取的半导体器件及其制造方法公开(公告)号：US09318327B2
公开(公告)日：2016-04-19
申请号：US11563712
申请日：2006-11-28
IPC分类号： H01L29/06 , H01L21/02 , H01L31/0236 , H01L33/00
CPC分类号： H01L21/02658 , H01L21/02378 , H01L21/02392 , H01L21/02395 , H01L21/02403 , H01L21/0242 , H01L21/02425 , H01L21/0254 , H01L31/0236 , H01L31/02363 , H01L33/007 , Y02E10/50
摘要： Semiconductor device structures are provided that are suitable for use in the fabrication of electronic devices such as light emitting diodes. The semiconductor device structures include a substrate having a roughened growth surface suitable for supporting the growth of an epitaxial region thereon. The device structure can include an epitaxial region having reduced defects and/or improved radiation extraction efficiency on the roughened growth surface of the substrate. The roughened growth surface of the substrate can have an average roughness Ra of at least about 1 nanometer (nm) and an average peak to valley height Rz of at least about 10 nanometers (nm).
摘要翻译： 提供了适用于制造诸如发光二极管的电子设备的半导体器件结构。 半导体器件结构包括具有适于支持其上的外延区域的生长的粗糙生长表面的衬底。 器件结构可以包括在衬底的粗糙化生长表面上具有减小的缺陷和/或改进的辐射提取效率的外延区域。 基底的粗糙化的生长表面可以具有至少约1纳米（nm）的平均粗糙度Ra和至少约10纳米（nm）的平均峰谷高度Rz。
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