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69 条记录 (耗时 0.031 秒)

    Ferroelectric memory devices and operating methods thereof
    1.
    发明授权
    Ferroelectric memory devices and operating methods thereof 有权
    铁电存储器件及其操作方法

    公开(公告)号：US08385098B2

    公开(公告)日：2013-02-26

    申请号：US12923131

    申请日：2010-09-03

    申请人： Ki-ha Hong ,  Jeong-seob Kim ,  Jai-kwang Shin

    发明人： Ki-ha Hong ,  Jeong-seob Kim ,  Jai-kwang Shin

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/11597 ,  H01L27/1203 ,  H01L29/1606 ,  H01L29/78391

    摘要： A ferroelectric memory device having a NAND array of a plurality of ferroelectric memory cells includes: a fully depleted channel layer; a gate electrode layer; and a ferroelectric layer located between the channel layer and the gate electrode layer. The data of the plurality of ferroelectric memory cells is erased by applying a first erase voltage to a bit line and a common source line and applying a second erase voltage to a string selection line and a ground selection line.

    摘要翻译： 具有多个铁电存储单元的NAND阵列的铁电存储器件包括：完全耗尽的沟道层; 栅电极层; 以及位于沟道层和栅电极层之间的铁电层。 通过对位线和公共源极线施加第一擦除电压并向串选择线和地选择线施加第二擦除电压来擦除多个铁电存储单元的数据。

    Ferroelectric memory devices and operating methods thereof
    2.
    发明申请
    Ferroelectric memory devices and operating methods thereof 有权
    铁电存储器件及其操作方法

    公开(公告)号：US20110075467A1

    公开(公告)日：2011-03-31

    申请号：US12923131

    申请日：2010-09-03

    申请人： Ki-ha Hong ,  Jeong-seob Kim ,  Jai-kwang Shin

    发明人： Ki-ha Hong ,  Jeong-seob Kim ,  Jai-kwang Shin

    IPC分类号： G11C11/22 ,  H01L29/82 ,  G11C7/00

    CPC分类号： G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/11597 ,  H01L27/1203 ,  H01L29/1606 ,  H01L29/78391

    摘要： A ferroelectric memory device having a NAND array of a plurality of ferroelectric memory cells includes: a fully depleted channel layer; a gate electrode layer; and a ferroelectric layer located between the channel layer and the gate electrode layer. The data of the plurality of ferroelectric memory cells is erased by applying a first erase voltage to a bit line and a common source line and applying a second erase voltage to a string selection line and a ground selection line.

    摘要翻译： 具有多个铁电存储单元的NAND阵列的铁电存储器件包括：完全耗尽的沟道层; 栅电极层; 以及位于沟道层和栅电极层之间的铁电层。 通过对位线和公共源极线施加第一擦除电压并向串选择线和地选择线施加第二擦除电压来擦除多个铁电存储单元的数据。

    Substrate structure, semiconductor device fabricated from the same, and method of fabricating the semiconductor device
    6.
    发明授权
    Substrate structure, semiconductor device fabricated from the same, and method of fabricating the semiconductor device 有权
    基板结构，由其制造的半导体器件以及半导体器件的制造方法

    公开(公告)号：US08921890B2

    公开(公告)日：2014-12-30

    申请号：US13551217

    申请日：2012-07-17

    申请人： Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin ,  Chang-yong Um ,  Jae-joon Oh ,  Jong-bong Ha ,  In-jun Hwang ,  Ki-ha Hong

    发明人： Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin ,  Chang-yong Um ,  Jae-joon Oh ,  Jong-bong Ha ,  In-jun Hwang ,  Ki-ha Hong

    IPC分类号： H01L31/102

    CPC分类号： H01L29/7813 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/41741 ,  H01L29/66734

    摘要： According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate.

    摘要翻译： 根据示例实施例，衬底结构可以包括GaN基第三材料层，GaN基第二材料层，GaN基第一材料层和非GaN基衬底上的缓冲层。 GaN基第一材料层可以掺杂有第一导电类型的杂质。 GaN基第二材料层可以以小于第一GaN基材料层中的第一导电类型杂质的密度的密度掺杂第二导电型杂质。 GaN基第三材料层可以以比GaN基第一材料层的第一导电类型杂质的密度小的密度掺杂第一导电型杂质。 在将第二衬底附着到衬底结构上之后，可以去除非GaN基衬底，并且可以在第二衬底上制造GaN基垂直型半导体器件。

    Method Of Manufacturing High Electron Mobility Transistor
    7.
    发明申请
    Method Of Manufacturing High Electron Mobility Transistor 有权
    制造高电子迁移率晶体管的方法

    公开(公告)号：US20110212582A1

    公开(公告)日：2011-09-01

    申请号：US13017361

    申请日：2011-01-31

    申请人： Ki-ha Hong ,  U-in Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    发明人： Ki-ha Hong ,  U-in Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    IPC分类号： H01L21/335

    CPC分类号： H01L29/402 ,  H01L29/0891 ,  H01L29/66462 ,  H01L29/7786

    摘要： A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.

    摘要翻译： 制造高电子迁移率晶体管（HEMT）的方法可以包括在衬底上形成具有不同晶格常数的第一和第二材料层，在第二材料层上形成源极，漏极和栅极，以及改变第二材料层 在栅极和漏极之间形成不同的材料层，或改变第二材料层的厚度，或在第二材料层上形成p型半导体层。 第二材料层的变化可以在栅极和漏极之间的第二材料层的整个区域中发生，或者仅在与栅极相邻的第二材料层的部分区域中发生。 p型半导体层可以形成在栅极和漏极之间的第二材料层的整个顶表面上，或者仅形成在与栅极相邻的顶表面的部分区域上。

    Power electronic devices, methods of manufacturing the same, and integrated circuit modules including the same
    9.
    发明授权
    Power electronic devices, methods of manufacturing the same, and integrated circuit modules including the same 有权
    电力电子装置及其制造方法以及包括其的集成电路模块

    公开(公告)号：US08513705B2

    公开(公告)日：2013-08-20

    申请号：US12923126

    申请日：2010-09-03

    申请人： Jong-seob Kim ,  Ki-ha Hong ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Whang ,  Jai-kwang Shin

    发明人： Jong-seob Kim ,  Ki-ha Hong ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Whang ,  Jai-kwang Shin

    IPC分类号： H01L29/778 ,  H01L21/335

    CPC分类号： H01L29/207 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

    摘要： Power electronic devices including 2-dimensional electron gas (2DEG) channels and methods of manufacturing the same. A power electronic device includes lower and upper material layers for forming a 2DEG channel, and a gate contacting an upper surface of the upper material layer. A region below the gate of the 2DEG channel is an off region where the density of a 2DEG is reduced or zero. The entire upper material layer may be continuous and may have a uniform thickness. A region of the upper material layer under the gate contains an impurity for reducing or eliminating a lattice constant difference between the lower and upper material layers.

    摘要翻译： 包括二维电子气体（2DEG）通道的电力电子装置及其制造方法。 电力电子设备包括用于形成2DEG通道的下部和上部材料层，以及与上部材料层的上表面接触的栅极。 2DEG通道的栅极下方的区域是2DEG的密度减小或为零的截止区域。 整个上部材料层可以是连续的并且可以具有均匀的厚度。 在栅极下方的上部材料层的区域包含用于减少或消除下部和上部材料层之间的晶格常数差的杂质。

    Spin field effect logic devices
    10.
    发明授权
    Spin field effect logic devices 有权
    旋转场效应逻辑器件

    公开(公告)号：US08487358B2

    公开(公告)日：2013-07-16

    申请号：US12654349

    申请日：2009-12-17

    申请人： Ki-ha Hong ,  Jong-seob Kim ,  Jai-kwang Shin

    发明人： Ki-ha Hong ,  Jong-seob Kim ,  Jai-kwang Shin

    IPC分类号： H01L29/82 ,  H01L29/94

    CPC分类号： H01L29/66984 ,  B82Y25/00 ,  H01F1/401 ,  H01F10/1936 ,  H01F10/3254

    摘要： Provided are spin field effect logic devices, the logic devices including: a gate electrode; a channel formed of a magnetic material above the gate electrode to selectively transmit spin-polarized electrons; a source on the channel; and a drain and an output electrode on the channel outputting electrons transmitted from the source. The gate electrode may control a magnetization state of the channel in order to selectively transmit the electrons injected from the source to the channel.

    摘要翻译： 提供的是自旋场效应逻辑器件，逻辑器件包括：栅电极; 由栅电极上方的磁性材料形成的沟道，以选择性地透射自旋极化电子; 频道上的来源; 以及沟道上的漏极和输出电极，输出从源极发射的电子。 栅电极可以控制通道的磁化状态，以选择性地将从源引入的电子传输到通道。