公开(公告)号：US20130023419A1

公开(公告)日：2013-01-24

申请号：US13543304

申请日：2012-07-06

申请人： Kiichiro MATSUSHITA ,  Hiroomi HANAI ,  Kazunori HAYASHI ,  Jun FUJIKI ,  Akihiro OOHASHI ,  Kayoko TAKAYANAGI ,  Kazumasa MUKOBATA ,  Yoshinori TANAKA

发明人： Kiichiro MATSUSHITA ,  Hiroomi HANAI ,  Kazunori HAYASHI ,  Jun FUJIKI ,  Akihiro OOHASHI ,  Kayoko TAKAYANAGI ,  Kazumasa MUKOBATA ,  Yoshinori TANAKA

IPC分类号： H01B12/04 ,  H01B3/00 ,  B32B27/28 ,  B32B33/00 ,  B32B7/00

CPC分类号： B32B27/281 ,  B32B25/08 ,  B32B27/08 ,  B32B2307/50 ,  B32B2307/51 ,  B32B2307/54 ,  B32B2457/00 ,  B32B2457/04 ,  H01B3/306 ,  H01B3/46 ,  Y10T428/24975 ,  Y10T428/31504 ,  Y10T428/31663 ,  Y10T428/31721

摘要： Provided is a covering material, in which the covering material is a covering material for covering a superconducting wire, a tensile strength at break thereof at −196° C. is 12.0 N/3 mm or more, and a tensile elongation at break thereof at −196° C. is 12% or more. The covering material preferably includes a backing made of a polyimide resin. The covering material preferably includes a viscoelastic layer formed on one surface of the backing.

摘要翻译： 提供一种覆盖材料，其中覆盖材料是用于覆盖超导线材的覆盖材料，其在-196℃下的断裂拉伸强度为12.0N / 3mm以上，其断裂拉伸伸长率为 -196℃为12％以上。 覆盖材料优选包括由聚酰亚胺树脂制成的背衬。 覆盖材料优选包括形成在背衬的一个表面上的粘弹性层。

公开(公告)号：US20130008685A1

公开(公告)日：2013-01-10

申请号：US13543344

申请日：2012-07-06

申请人： Kiichiro MATSUSHITA ,  Hiroomi HANAI ,  Kazunori HAYASHI ,  Jun FUJIKI ,  Akihiro OOHASHI ,  Kayoko TAKAYANAGI ,  Kazumasa MUKOBATA

发明人： Kiichiro MATSUSHITA ,  Hiroomi HANAI ,  Kazunori HAYASHI ,  Jun FUJIKI ,  Akihiro OOHASHI ,  Kayoko TAKAYANAGI ,  Kazumasa MUKOBATA

IPC分类号： H01B7/00 ,  H01B17/00

CPC分类号： H01B3/46

摘要： Provided is a covering material, which includes a backing having an upper surface and a lower surface opposite to the upper surface, and a viscoelastic layer formed on the upper surface of the backing, in which the covering material is a covering material for covering a rectangular electric wire, and an adhesive force of the viscoelastic layer to the lower surface of the backing as measured by peeling at a peeling angle of 180° and a tensile rate of 300 mm/min is 0.05 N/20 mm or more and 10 N/20 mm or less. A covered rectangular electric wire includes the covering material and a rectangular electric wire covered with the covering material. An electrical device is produced by using the covered rectangular electric wire.

摘要翻译： 提供一种覆盖材料，其包括具有上表面和与上表面相对的下表面的背衬，以及形成在背衬的上表面上的粘弹性层，其中覆盖材料是用于覆盖矩形的覆盖材料 电线以及通过在180°的剥离角度和300mm / min的拉伸速度下剥离测定的粘弹性层对背衬的下表面的粘合力为0.05N / 20mm以上且10N / 20mm以下。 覆盖的矩形电线包括覆盖材料和覆盖有覆盖材料的矩形电线。 通过使用覆盖的矩形电线制造电气设备。

公开(公告)号：US20130234231A1

公开(公告)日：2013-09-12

申请号：US13560260

申请日：2012-07-27

申请人： Jun FUJIKI ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Jun FUJIKI ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body, a second insulating layer, a select gate, a memory hole, a memory film, a channel body, a first semiconductor layer, and a second semiconductor layer. The select gate is provided on the second insulating layer. The memory film is provided on an inner wall of the memory hole. The channel body is provided inside the memory film. The first semiconductor layer is provided on an upper surface of the channel body. The second semiconductor layer is provided on the first semiconductor layer. The first semiconductor layer contains silicon germanium. The second semiconductor layer contains silicon germanium doped with a first impurity. A boundary between the first semiconductor layer and the second semiconductor layer is provided above a position of an upper end of the select gate.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括层叠体，第二绝缘层，选择栅极，存储器孔，存储​​膜，通道体，第一半导体层和第二半导体层。 选择栅极设置在第二绝缘层上。 记忆膜设置在存储孔的内壁上。 通道体设置在记忆膜的内部。 第一半导体层设置在通道主体的上表面上。 第二半导体层设置在第一半导体层上。 第一半导体层包含硅锗。 第二半导体层包含掺杂有第一杂质的硅锗。 第一半导体层和第二半导体层之间的边界设置在选择栅极的上端的位置的上方。

公开(公告)号：US20130037776A1

公开(公告)日：2013-02-14

申请号：US13425687

申请日：2012-03-21

申请人： Yoshifumi NISHI ,  Hidenori MIYAGAWA ,  Daisuke MATSUSHITA ,  Jun FUJIKI ,  Takeshi IMAMURA

发明人： Yoshifumi NISHI ,  Hidenori MIYAGAWA ,  Daisuke MATSUSHITA ,  Jun FUJIKI ,  Takeshi IMAMURA

IPC分类号： H01L45/00

CPC分类号： H01L45/085 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/149

摘要： A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.

摘要翻译： 根据实施例的可变电阻存储器包括：第一布线; 与第一布线相交的第二布线; 设置在所述第一布线和所述第二布线之间的交叉区域中的第一电极，所述第一电极连接到所述第一布线; 连接到第二布线的第二电极，第二电极面对第一电极; 设置在所述第一电极和所述第二电极之间的可变电阻层; 以及形成在第二电极的侧部的第一绝缘层和第一半导体层中的一个。 第一绝缘层和第一半导体层中的一个，第二电极形状在第二电极的侧部空隙。

公开(公告)号：US20120068159A1

公开(公告)日：2012-03-22

申请号：US13070108

申请日：2011-03-23

申请人： Jun FUJIKI ,  Naoki Yasuda ,  Daisuke Matsushita

发明人： Jun FUJIKI ,  Naoki Yasuda ,  Daisuke Matsushita

IPC分类号： H01L29/08 ,  H01L29/792 ,  B82Y99/00

CPC分类号： H01L29/792 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first memory portion. The first memory portion includes a first base semiconductor layer, a first electrode, a first channel semiconductor layer, a first base tunnel insulating film, a first channel tunnel insulating, a first charge retention layer and a first block insulating film. The first channel semiconductor layer is provided between the first base semiconductor layer and the first electrode, and includes a first channel portion. The first base tunnel insulating film is provided between the first base semiconductor layer and the first channel semiconductor layer. The first channel tunnel insulating film is provided between the first electrode and the first channel portion. The first charge retention layer is provided between the first electrode and the first channel tunnel insulating film. The first block insulating film is provided between the first electrode and the first charge retention layer.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一存储器部分。 第一存储部分包括第一基极半导体层，第一电极，第一沟道半导体层，第一基极隧道绝缘膜，第一沟道隧道绝缘，第一电荷保持层和第一块绝缘膜。 第一沟道半导体层设置在第一基底半导体层和第一电极之间，并且包括第一沟道部分。 第一基极隧道绝缘膜设置在第一基极半导体层和第一沟道半导体层之间。 第一通道隧道绝缘膜设置在第一电极和第一沟道部分之间。 第一电荷保持层设置在第一电极和第一沟道隧道绝缘膜之间。 第一块绝缘膜设置在第一电极和第一电荷保持层之间。

公开(公告)号：US20090244984A1

公开(公告)日：2009-10-01

申请号：US12268648

申请日：2008-11-11

申请人： Jun FUJIKI

发明人： Jun FUJIKI

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/115 ,  G11C11/5628 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11521 ,  H01L29/792

摘要： A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, and changes its data memory state by injection of charges into the floating electrode. The method includes to achieve a state in which charges having a first polarity are injected into the floating electrode: providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the second insulating film; subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film; and subsequently providing a third potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode.

摘要翻译： 提供一种用于驱动非易失性半导体存储器件的方法。 非易失性半导体存储器件包括具有通道的半导体层，设置在沟道上的第一绝缘膜，设置在第一绝缘膜上的浮置电极，设置在浮置电极上的第二绝缘膜，以及设置在第二绝缘膜上的栅电极 绝缘膜，并通过将电荷注入浮动电极来改变其数据存储状态。 该方法包括实现将具有第一极性的电荷注入到浮置电极中的状态：在半导体层和栅电极之间提供第一电位差以将具有第一极性的电荷注入到第二绝缘膜中; 随后在半导体层和栅电极之间提供第二电位差，以将具有与第一极性相反的第二极性的电荷注入第二绝缘膜; 并且随后在半导体层和栅电极之间提供第三电位差，以将具有第一极性的电荷注入到浮置电极中。

公开(公告)号：US20130010535A1

公开(公告)日：2013-01-10

申请号：US13619223

申请日：2012-09-14

申请人： Masao SHINGU ,  Jun FUJIKI ,  Naoki YASUDA ,  Koichi MURAOKA

发明人： Masao SHINGU ,  Jun FUJIKI ,  Naoki YASUDA ,  Koichi MURAOKA

IPC分类号： H01L29/792 ,  G11C11/40

CPC分类号： H01L29/7883 ,  G11C11/40 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/788 ,  H01L29/792

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.

公开(公告)号：US20120069679A1

公开(公告)日：2012-03-22

申请号：US13239964

申请日：2011-09-22

申请人： Jun FUJIKI ,  Naoki Yasuda ,  Koichi Muraoka

发明人： Jun FUJIKI ,  Naoki Yasuda ,  Koichi Muraoka

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory string including a plurality of memory cells and, a driving unit. In sequentially reading data stored in the memory cells by applying a first signal to the memory cells, a second signal is applied to a second cell. The driving unit applies a third signal to the gate electrodes of all the memory cells prior to the sequential reading. The third signal has a voltage smaller than the second signal and time duration equal to or more than that of a sum of time duration during which the first signal is applied to all the memory cells. In a period prior to the third signal application, the driving unit performs at least one of applying a fourth signal to the gate electrodes and matching a potential of the gate electrodes with that of the semiconductor layer.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括包括多个存储单元的存储器串和驱动单元。 通过向存储单元施加第一信号来顺序读取存储在存储单元中的数据，第二信号被施加到第二单元。 驱动单元在顺序读取之前将所有存储单元的栅电极施加第三信号。 第三信号的电压小于第二信号，并且持续时间等于或大于将第一信号施加到所有存储器单元的持续时间之和的电平。 在第三信号施加之前的时段中，驱动单元执行将第四信号施加到栅电极并使栅电极的电位与半导体层的电位相匹配中的至少一个。

公开(公告)号：US20110199834A1

公开(公告)日：2011-08-18

申请号：US13094534

申请日：2011-04-26

申请人： Jun FUJIKI

发明人： Jun FUJIKI

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483

摘要： A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device has source/drain diffusion layers spaced from each other in a surface portion of a semiconductor substrate, a laminated insulating film formed on a channel between the source/drain diffusion layers and including a charge storage layer, and a gate electrode formed on the laminated insulating film, the nonvolatile semiconductor memory device changing its data memory state by injection of charges into the charge storage layer. The method includes, before injecting charges to change the data memory state into the charge storage layer: injecting charges having a polarity identical to that of the charges to be injected; and further injecting charges having a polarity opposite to that of the injected charges.

摘要翻译： 提供一种用于驱动非易失性半导体存储器件的方法。 非易失性半导体存储器件在半导体衬底的表面部分中具有彼此间隔开的源极/漏极扩散层，形成在源极/漏极扩散层之间并且包括电荷存储层的沟道上的层叠绝缘膜，以及栅电极 形成在层叠绝缘膜上的非易失性半导体存储器件通过将电荷注入电荷存储层来改变其数据存储状态。 该方法包括：在注入电荷以将数据存储状态改变为电荷存储层之前，注入具有与要注入的电荷相同极性的电荷; 并且进一步注入与注入的电荷的极性相反极性的电荷。

公开(公告)号：US20100080065A1

公开(公告)日：2010-04-01

申请号：US12496064

申请日：2009-07-01

申请人： Jun FUJIKI ,  Koichi Muraoka ,  Naoki Yasuda

发明人： Jun FUJIKI ,  Koichi Muraoka ,  Naoki Yasuda

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： H01L29/7881 ,  G11C16/0466 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/792

摘要： A nonvolatile semiconductor memory device includes a memory cell and a driving unit. The a memory cell has a semiconductor layer having, a channel, and a source region and a drain region provided on both sides of the channel; a first insulating film provided on the channel; a charge retention layer provided on the first insulating film; and a gate electrode provided on the charge retention layer. The driving unit applies a burst signal having a constant amplitude and a constant frequency between the gate electrode and the semiconductor layer and performs at least one of operations of programming and erasing charge on the charge retention layer.

摘要翻译： 非易失性半导体存储器件包括存储单元和驱动单元。 存储单元具有半导体层，具有设置在沟道两侧的沟道以及源极区和漏极区; 设置在所述通道上的第一绝缘膜; 设置在所述第一绝缘膜上的电荷保持层; 以及设置在电荷保持层上的栅电极。 驱动单元在栅电极和半导体层之间施加具有恒定幅度和恒定频率的突发​​信号，并执行对电荷保持层进行编程和擦除电荷的操作中的至少一种。