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    Semiconductor memory and controller with time-shared mode for row address, column address and data mask signals inputted via address terminals
    3.
    发明授权
    Semiconductor memory and controller with time-shared mode for row address, column address and data mask signals inputted via address terminals 失效
    具有时域共享模式的半导体存储器和控制器，用于通过地址端子输入的行地址，列地址和数据掩码信号

    公开(公告)号：US07684258B2

    公开(公告)日：2010-03-23

    申请号：US11705405

    申请日：2007-02-13

    申请人： Tatsuya Kanda ,  Kotoku Sato

    发明人： Tatsuya Kanda ,  Kotoku Sato

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1006 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4096

    摘要： To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal. Namely, the first data mask signal is supplied to the address terminal at a different timing from timing at which the first and second address signals are received. The first address signal, second address signal, and first data mask signal are output, for example, from a controller accessing a semiconductor memory. A data input/output circuit inputs/outputs data via a data terminal and masks at least either of write data to memory cells and read data from the memory cells in accordance with logic of the first data mask signal.

    摘要翻译： 即使当数据屏蔽信号中的位数较大时，即使在数据屏蔽信号中的位数较大的情况下，也可以不增加外部端子的数量来执行数据信号的屏蔽控制，地址输入电路顺序地接收第一地址信号，第二地址信号和第一数据屏蔽信号 与时钟信号的过渡沿同步地提供给地址终端。 即，第一数据屏蔽信号以与接收第一和第二地址信号的定时不同的定时提供给地址终端。 例如，第一地址信号，第二地址信号和第一数据掩码信号从访问半导体存储器的控制器输出。 数据输入/输出电路通过数据端口输入/输出数据，并根据第一数据屏蔽信号的逻辑，将写数据中的至少一个写入存储单元并从存储单元读取数据。

    Memory device, memory controller and memory system
    4.
    发明申请
    Memory device, memory controller and memory system 有权
    内存设备，内存控制器和内存系统

    公开(公告)号：US20080151677A1

    公开(公告)日：2008-06-26

    申请号：US11698286

    申请日：2007-01-26

    申请人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

    发明人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

    IPC分类号： G11C8/12

    CPC分类号： G11C11/4087 ,  G09G5/393 ,  G09G5/395 ,  G11C8/12

    摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

    摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

    Semiconductor memory having test function for refresh operation
    5.
    发明授权
    Semiconductor memory having test function for refresh operation 有权
    半导体存储器具有刷新操作的测试功能

    公开(公告)号：US07114025B2

    公开(公告)日：2006-09-26

    申请号：US10689486

    申请日：2003-10-21

    申请人： Tatsuya Kanda ,  Akihiro Funyu ,  Takahiko Sato ,  Yoshiaki Okuyama ,  Jun Ohno ,  Hitoshi Ikeda

    发明人： Tatsuya Kanda ,  Akihiro Funyu ,  Takahiko Sato ,  Yoshiaki Okuyama ,  Jun Ohno ,  Hitoshi Ikeda

    IPC分类号： G11C7/00 ,  G06F13/00

    CPC分类号： G11C11/406 ,  G11C11/401 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50016

    摘要： A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.

    摘要翻译： 半导体存储器包括刷新定时器和用于确定访问操作和刷新操作之间的优先级顺序的仲裁器，以便自动执行存储器内的刷新操作。 检测电路在测试模式下工作，并且在执行刷新操作之前发生新的内部刷新请求时，输出指示刷新操作尚未执行的检测信号。 例如，当访问请求的间隔短并且在访问操作之间不能插入刷新操作时，输出检测信号。 也就是说，在自动执行刷新操作的半导体存储器中，可以评估提供访问请求的最小间隔。 结果，随着半导体存储器的显影周期的减少，可以减少评估时间。

    Semiconductor memory
    6.
    发明申请
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US20050146968A1

    公开(公告)日：2005-07-07

    申请号：US11057841

    申请日：2005-02-15

    申请人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

    发明人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

    IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C29/02

    CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

    摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

    摘要翻译： 响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。 刷新操作在访问请求与刷新请求之间发生冲突时结束。 因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。 可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。 由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。 结果，可以减少半导体存储器的显影周期。

    Self-test circuit and memory device incorporating it
    7.
    发明授权
    Self-test circuit and memory device incorporating it 有权
    自检电路和结合其的存储器件

    公开(公告)号：US06907555B1

    公开(公告)日：2005-06-14

    申请号：US09691115

    申请日：2000-10-19

    申请人： Yukihiro Nomura ,  Hiroyuki Fujimoto ,  Takahiro Suzuki ,  Tatsuya Kanda ,  Yasurou Matsuzaki ,  Masahiko Saitou ,  Hiroyoshi Tomita

    发明人： Yukihiro Nomura ,  Hiroyuki Fujimoto ,  Takahiro Suzuki ,  Tatsuya Kanda ,  Yasurou Matsuzaki ,  Masahiko Saitou ,  Hiroyoshi Tomita

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F12/16 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/12 ,  G11C29/44

    CPC分类号： G11C29/44

    摘要： The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.

    摘要翻译： 本发明是一种结合在存储器件中的自检电路（BIST），其响应于来自外部的测试激活信号被激活。 当该自检电路响应于来自外部的测试激活信号（WBIZ）被激活时，它产生测试操作命令（WBI-CMD），生成测试地址（WBI-ADD），并生成测试数据（WBI- 数据）。 此外，在自检电路将测试数据写入存储单元之后，进行比较以确定从该存储单元读取的读取数据是否与写入的测试数据相同并存储信息 关于这个比较的结果。 然后将该比较结果信息输出到外部。

    Semiconductor device reconciling different timing signals
    8.
    发明授权
    Semiconductor device reconciling different timing signals 有权
    半导体器件协调不同的定时信号

    公开(公告)号：US06292428B1

    公开(公告)日：2001-09-18

    申请号：US09240007

    申请日：1999-01-29

    申请人： Hiroyoshi Tomita ,  Tatsuya Kanda

    发明人： Hiroyoshi Tomita ,  Tatsuya Kanda

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C8/00 ,  G11C8/04 ,  G11C8/18

    摘要： A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.

    摘要翻译： 与时钟信号同步地接收地址并与选通信号同步地接收数据的半导体器件包括地址锁存电路，响应于时钟信号依次选择地址锁存电路之一的第一控制电路，以及 控制所选择的一个地址锁存电路以响应于时钟信号锁存对应的一个地址;以及第二控制电路，其响应于选通信号依次选择一个地址锁存电路，并且控制 所选择的一个地址锁存电路响应于选通信号输出对应的一个地址。

    Semiconductor memory
    10.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US07471585B2

    公开(公告)日：2008-12-30

    申请号：US11508917

    申请日：2006-08-24

    申请人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

    发明人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

    IPC分类号： G11C7/00

    CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

    摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

    摘要翻译： 响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。 刷新操作在访问请求与刷新请求之间发生冲突时结束。 因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。 可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。 由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。 结果，可以减少半导体存储器的显影周期。