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公开(公告)号：US07666728B2
公开(公告)日：2010-02-23
申请号：US12028593
申请日：2008-02-08
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205 , H01L21/4763 , H01L21/302
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76832 , H01L21/76834 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7842
摘要： A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成栅极绝缘膜和由多晶硅制成的栅电极; 将离子注入到半导体衬底中以形成作为源极或漏极的半导体区域; 在所述半导体衬底上形成钴膜和氮化钛膜以覆盖所述栅电极; 进行退火以引起Co和Si之间的反应以及半导体区域以形成CoSi层; 进行湿式清洗以除去氮化钛膜和未反应的钴膜，使CoSi层离开栅电极和半导体区域; 进行退火以引起CoSi层与栅极电极和半导体区域之间的反应以形成CoSi 2层; 进行HPM清洗; 以及通过低压CVD在半导体衬底上形成氮化硅膜以覆盖栅电极。
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公开(公告)号：US07348230B2
公开(公告)日：2008-03-25
申请号：US11008276
申请日：2004-12-10
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76832 , H01L21/76834 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7842
摘要： A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成栅极绝缘膜和由多晶硅制成的栅电极; 将离子注入到半导体衬底中以形成作为源极或漏极的半导体区域; 在所述半导体衬底上形成钴膜和氮化钛膜以覆盖所述栅电极; 进行退火以引起Co和Si之间的反应以及半导体区域以形成CoSi层; 进行湿式清洗以除去氮化钛膜和未反应的钴膜，使CoSi层离开栅极电极和半导体区域; 进行退火以引起CoSi层和栅极电极和半导体区域之间的反应以形成CoSi 2 O 3层; 进行HPM清洗; 以及通过低压CVD在半导体衬底上形成氮化硅膜以覆盖栅电极。
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公开(公告)号：US20050145897A1
公开(公告)日：2005-07-07
申请号：US11008276
申请日：2004-12-10
IPC分类号： H01L21/28 , H01L21/285 , H01L21/304 , H01L21/318 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L23/522 , H01L27/092 , H01L29/417 , H01L29/78 , H01L21/3205 , H01L29/76 , H01L31/062
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76832 , H01L21/76834 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7842
摘要： A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成栅极绝缘膜和由多晶硅制成的栅电极; 将离子注入到半导体衬底中以形成作为源极或漏极的半导体区域; 在所述半导体衬底上形成钴膜和氮化钛膜以覆盖所述栅电极; 进行退火以引起Co和Si之间的反应以及半导体区域以形成CoSi层; 进行湿式清洗以除去氮化钛膜和未反应的钴膜，使CoSi层离开栅电极和半导体区域; 进行退火以引起CoSi层和栅极电极和半导体区域之间的反应以形成CoSi 2 O 3层; 进行HPM清洗; 以及通过低压CVD在半导体衬底上形成氮化硅膜以覆盖栅电极。
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公开(公告)号：US20080142901A1
公开(公告)日：2008-06-19
申请号：US12028593
申请日：2008-02-08
IPC分类号： H01L27/088
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76832 , H01L21/76834 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7842
摘要： A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.
摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成栅极绝缘膜和由多晶硅制成的栅电极; 将离子注入到半导体衬底中以形成作为源极或漏极的半导体区域; 在所述半导体衬底上形成钴膜和氮化钛膜以覆盖所述栅电极; 进行退火以引起Co和Si之间的反应以及半导体区域以形成CoSi层; 进行湿式清洗以除去氮化钛膜和未反应的钴膜，使CoSi层离开栅电极和半导体区域; 进行退火以引起CoSi层与栅极电极和半导体区域之间的反应以形成CoSi 2层; 进行HPM清洗; 以及通过低压CVD在半导体衬底上形成氮化硅膜以覆盖栅电极。
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公开(公告)号：US06403446B1
公开(公告)日：2002-06-11
申请号：US09536447
申请日：2000-03-28
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S148/05
摘要： Manufacturing a semiconductor device avoiding an increase of transistor leak current or reduction of the withstanding voltage characteristics is by at least one of: The pad oxide film is removed along the substrate surface from the upper edge of the groove over a distance ranging from 5 to 40 nm: The exposed surface of the semiconductor substrate undergoes removal by isotropic etching within 20 nm; and oxidizing a groove portion formed in a semiconductor substrate in an oxidation environment with a gas ratio of hydrogen (H2) to oxygen (O2) being less than or equal to 0.5, an increase of the curvature radius beyond 3nm is achieved without associating the risk of creation of any level difference on the substrate surface at or near the upper groove edge portions in a groove separation structure. This eliminates either an increase of transistor leak current or reduction of the withstanding voltage characteristics thereof otherwise occurring due to local electric field concentration near or around the terminate ends of a gate electrode film which in turn leads to an ability to improve electrical reliability of transistors used.
摘要翻译： 制造半导体器件避免晶体管泄漏电流的增加或耐压特性的降低是至少以下之一：衬垫氧化膜沿着衬底表面从沟槽的上边缘移除5至40的距离 nm：通过各向同性蚀刻在20nm内去除半导体衬底的暴露表面; 并且在氧（H2）与氧气（O2）的气体比小于或等于0.5的氧化环境中氧化形成在半导体衬底中的沟槽部分，实现曲率半径超过3nm的增加，而不会使风险 在槽分离结构中的上槽边缘部分处或附近在基板表面上产生任何水平差。 这消除了晶体管泄漏电流的增加或由于栅极电极膜的端部附近或周围的局部电场浓度而导致的耐压特性的降低，这进而导致提高使用的晶体管的电可靠性的能力 。
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公开(公告)号：US6090684A
公开(公告)日：2000-07-18
申请号：US363184
申请日：1999-07-29
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
IPC分类号： H01L21/76 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H.sub.2) to oxygen (O.sub.2) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.
摘要翻译： 浅沟隔离结构（SGI）使半导体衬底上的相邻晶体管电绝缘。 在半导体基板上形成衬垫氧化膜，在衬垫氧化膜上形成氧化抑制膜。 除去氧化物抑制膜和垫氧化膜的一部分以形成槽。 特别地，在5〜40nm的范围内，从槽的上边缘去除衬垫氧化膜。 凹槽的区域在氢（H 2）与氧（O 2）的铸造比小于或等于0.5的氧化环境中被氧化。 在该比例下，在基板的上槽边缘处的低应力下氧化进行，从而能够在上槽边缘的四舍五入，而不会在基板表面上的上槽边缘处或附近产生水平差。
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公开(公告)号：US07045864B2
公开(公告)日：2006-05-16
申请号：US10170432
申请日：2002-06-14
申请人： Kota Funayama , Yasuko Yoshida , Masaru Nakamichi , Akio Nishida
发明人： Kota Funayama , Yasuko Yoshida , Masaru Nakamichi , Akio Nishida
IPC分类号： H01L29/76
CPC分类号： H01L27/11 , H01L21/823814 , H01L21/823835 , H01L27/092 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A semiconductor integrated circuit device, e.g., a memory cell of an SRAM, is formed of a pair of inverters having their input and output points connected in a crisscross manner and being formed of drive n-channel MISFETs and load p-channel MISFETs. The n-channel MISFETs and p-channel MISFETs have their back gates supplied with power supply voltage and a ground voltage, respectively. The MISFETs are formed with a metal silicide layer on the gate electrodes G and source regions (hatched areas) and without the formation of a metal silicide layer on the drain regions, respectively, whereby the leakage current of the MISFETs due to a voltage difference between the drain regions and wells can be reduced, and, thus, the power consumption can be reduced.
摘要翻译： 诸如SRAM的存储单元的半导体集成电路器件由一对反相器形成，它们的输入和输出点以十字交叉的方式连接并且由驱动n沟道MISFET和负载p沟道MISFET形成。 n沟道MISFET和p沟道MISFET分别具有电源电压和接地电压的后门。 MISFET在栅极电极G和源极区域（阴影区域）上形成有金属硅化物层，并且在漏极区域上不形成金属硅化物层，由此由于MISFET的漏电流由于 可以减少漏区和阱，从而可以降低功耗。
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公开(公告)号：US07414117B2
公开(公告)日：2008-08-19
申请号：US10795436
申请日：2004-03-09
申请人： Isao Saito , Akimitsu Okamoto , Yoshio Saito , Yasuko Yoshida , Kousuke Niwa
发明人： Isao Saito , Akimitsu Okamoto , Yoshio Saito , Yasuko Yoshida , Kousuke Niwa
CPC分类号： C07H19/04 , C07H19/06 , C07H19/067 , C07H19/16 , C07H21/00 , C07H21/04 , C12Q1/6837 , Y10S436/809 , C12Q2565/549
摘要： A novel nucleotide derivative, in case of existing as a member of a single-stranded sequence, undergoing a change in the fluorescent signal intendity depending on the corresponding base type in the partner strand with which the single-stranded sequence is hybridized, and which is a thymin/uracil derivative (1) emitting light most intensely when a confronting base in the partner strand with which the single-stranded nucleotide sequence is hybridized is adenine; a cytosine derivative (2) emitting light most intensely when the confronting base is guanine; an adenine derivative (3) emitting light most intensely when the confronting base is cytosine; a guanine derivative (4) emitting light most intensely when the confronting base is cytosine or thymine/uracil; and an adrnine derivative (5) emitting light most intensely when the confronting base is thymine/uracil/.
摘要翻译： 在存在单链序列成员的情况下，新的核苷酸衍生物依赖于与单链序列杂交的伴侣链中的相应碱基类型而经历荧光信号意图的变化，并且其是 当与单链核苷酸序列杂交的伴侣链中的相对的碱基是腺嘌呤时，最强烈地发射光的甲氨喋呤/尿嘧啶衍生物（1） 当相对的碱是鸟嘌呤时，胞嘧啶衍生物（2）最强地发射光; 当面对的碱基是胞嘧啶时，腺苷衍生物（3）最强地发光; 当面对的碱基是胞嘧啶或胸腺嘧啶/尿嘧啶时，最强烈地发射光的鸟嘌呤衍生物（4） 和当相对底物是胸腺嘧啶/尿嘧啶时最强烈地发光的腺苷衍生物（5）。
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公开(公告)号：US20080070795A1
公开(公告)日：2008-03-20
申请号：US11851865
申请日：2007-09-07
申请人： Keisuke Makino , Tsutomu Kodaki , Seiya Watanabe , Seung Pack , Mitsuru Nonogawa , Hiroo Wada , Yasuko Yoshida , Kazunari Yamada
发明人： Keisuke Makino , Tsutomu Kodaki , Seiya Watanabe , Seung Pack , Mitsuru Nonogawa , Hiroo Wada , Yasuko Yoshida , Kazunari Yamada
CPC分类号： C07D498/04 , C07H19/24 , C07H21/04
摘要： The present invention aims to provide a technique for stably immobilizing a probe on a carrier The present invention provides a linker compound represented by formula (1): wherein A represents a hydrogen atom, another substituent, a sugar, or a derivative thereof.
摘要翻译： 本发明的目的在于提供一种用于将探针稳定地固定在载体上的技术。本发明提供由式（1）表示的连接剂化合物：其中A表示氢原子，另一取代基，糖或其衍生物。
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10.发明申请公开(公告)号：US20060128094A1
公开(公告)日：2006-06-15
申请号：US11342695
申请日：2006-01-31
申请人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
发明人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
IPC分类号： H01L21/8242
CPC分类号： H01L27/11 , H01L27/1104
摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。
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