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1.发明申请公开(公告)号：US20090172681A1
公开(公告)日：2009-07-02
申请号：US11965953
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
IPC分类号： G06F9/46
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于时钟使能（CKE）协调的系统，方法和装置。 在一些实施例中，存储器控制器包括用于预测排定的请求是否将被发布到等级的逻辑。 存储器控制器还可以包括用于预测排定的请求是否将不被发布到等级的逻辑。 在一些实施例中，时钟使能（CKE）至少部分地基于预测被断言或取消断言为等级。 描述和要求保护其他实施例。
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2.发明授权公开(公告)号：US08429367B2
公开(公告)日：2013-04-23
申请号：US11965953
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
IPC分类号： G06F1/04
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于时钟使能（CKE）协调的系统，方法和装置。 在一些实施例中，存储器控制器包括用于预测排定的请求是否将被发布到等级的逻辑。 存储器控制器还可以包括用于预测排定的请求是否将不被发布到等级的逻辑。 在一些实施例中，时钟使能（CKE）至少部分地基于预测被断言或取消断言为等级。 描述和要求保护其他实施例。
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公开(公告)号：US20080244291A1
公开(公告)日：2008-10-02
申请号：US11728993
申请日：2007-03-28
申请人： James W. Alexander , Krishna Kant , Rahul Khanna
发明人： James W. Alexander , Krishna Kant , Rahul Khanna
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for a resource power controller. In some embodiments, an integrated circuit includes a resource power controller to control whether a resource is in an up state or a down state. In some embodiments, the resource power controller heuristically estimates when to return the resource to an up state based, at least in part, on an estimate of a gap size.
摘要翻译： 本发明的实施例一般涉及用于资源功率控制器的系统，方法和装置。 在一些实施例中，集成电路包括资源功率控制器，用于控制资源是处于向上状态还是处于向下状态。 在一些实施例中，资源功率控制器至少部分地基于间隙大小的估计来启发式地估计什么时候将资源返回到上升状态。
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公开(公告)号：US07885914B2
公开(公告)日：2011-02-08
申请号：US11965955
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
IPC分类号： G06N5/02
CPC分类号： G06N5/02
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于秩协调的系统，方法和装置。 在一些实施例中，主机包括秩协调逻辑。 秩协调逻辑可以包括性能测量逻辑，以至少部分地基于存储器通道的性能来测量存储器通道的性能和停留周期控制逻辑以选择驻留时间的长度。 描述和要求保护其他实施例。
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5.发明申请HARDWARE PROACTIVE IMPLEMENTATION FOR ACTIVE MODE POWER CONTROL OF PLATFORM RESOURCES 审中-公开用于平台资源的主动模式功率控制的硬件实现实现公开(公告)号：US20090172441A1
公开(公告)日：2009-07-02
申请号：US11967912
申请日：2007-12-31
申请人： Krishna Kant , James W. Alexander
发明人： Krishna Kant , James W. Alexander
IPC分类号： G06F1/00
CPC分类号： G06F1/3228
摘要： In some embodiments, estimating a duration of an idle period gap of a lower power state of a resource by exponentially smoothing successive idle period gaps. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，通过指数平滑连续的空闲周期间隙来估计资源的较低功率状态的空闲周期间隔的持续时间。 描述和要求保护其他实施例。
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6.发明授权Resource power controller to return a resource to an up state based on an estimate of a size of a gap in data traffic 有权资源功率控制器，用于基于数据业务中的间隙大小的估计将资源返回到上行状态公开(公告)号：US07865753B2
公开(公告)日：2011-01-04
申请号：US11728993
申请日：2007-03-28
申请人： James W. Alexander , Krishna Kant , Rahul Khanna
发明人： James W. Alexander , Krishna Kant , Rahul Khanna
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for a resource power controller. In some embodiments, an integrated circuit includes a resource power controller to control whether a resource is in an up state or a down state. In some embodiments, the resource power controller heuristically estimates when to return the resource to an up state based, at least in part, on an estimate of a gap size.
摘要翻译： 本发明的实施例一般涉及用于资源功率控制器的系统，方法和装置。 在一些实施例中，集成电路包括资源功率控制器，用于控制资源是处于向上状态还是处于向下状态。 在一些实施例中，资源功率控制器至少部分地基于间隙大小的估计来启发式地估计什么时候将资源返回到上升状态。
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公开(公告)号：US20090172440A1
公开(公告)日：2009-07-02
申请号：US11967873
申请日：2007-12-31
申请人： Krishna Kant , James W. Alexander
发明人： Krishna Kant , James W. Alexander
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3225 , G06F1/3275 , Y02D10/14
摘要： In some embodiments if a new request appears in a receive queue relating to a resource, and a controlled direction of the resource is in a low power state, a method starts an exit of the controlled direction after a delay. If receive direction of power control of the resource is in a low power state and preparation is being made to enter a low power state at the controlled direction, then the method decreases a watch and wait period that occurs prior to moving into the low power state at the controlled direction. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，如果在与资源相关的接收队列中出现新请求，并且资源的受控方向处于低功率状态，则方法在延迟之后开始退出受控方向。 如果资源的功率控制的接收方向处于低功率状态并且准备在受控方向进入低功率状态，则该方法减少在进入低功率状态之前发生的监视和等待周期 在受控方向。 描述和要求保护其他实施例。
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公开(公告)号：US20090171875A1
公开(公告)日：2009-07-02
申请号：US11965955
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
IPC分类号： G06N5/02
CPC分类号： G06N5/02
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于秩协调的系统，方法和装置。 在一些实施例中，主机包括秩协调逻辑。 秩协调逻辑可以包括性能测量逻辑，以至少部分地基于存储器通道的性能来测量存储器通道的性能和停留周期控制逻辑以选择驻留时间的长度。 描述和要求保护其他实施例。
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公开(公告)号：US20150169224A1
公开(公告)日：2015-06-18
申请号：US14109534
申请日：2013-12-17
申请人： James W. Alexander , Devadatta V. Bodas , Muralidhar Rajappa , Ramkumar Nagappan , Andy Hoffman
发明人： James W. Alexander , Devadatta V. Bodas , Muralidhar Rajappa , Ramkumar Nagappan , Andy Hoffman
IPC分类号： G06F3/06
CPC分类号： G06F3/065 , G06F3/0614 , G06F3/0622 , G06F3/0673 , G06F12/0223 , G06F12/0804 , G06F12/14 , G06F12/1425 , G06F21/74 , G06F21/79 , G06F2212/1024
摘要： Mechanisms for exposing a protected memory address are provided. A processing device may store a data value at a protected memory address. The protected memory address may be a control register or a status register. The processing device may identify a mirror relationship between the protected memory address and an unprotected memory address and copy the data value from the protected memory address to the unprotected memory address. The unprotected memory address may be directly accessible via an external interface.
摘要翻译： 提供暴露受保护的存储器地址的机制。 处理设备可以将数据值存储在受保护的存储器地址处。 受保护的存储器地址可以是控制寄存器或状态寄存器。 处理设备可以识别受保护的存储器地址和未受保护的存储器地址之间的镜像关系，并将数据值从受保护的存储器地址复制到未受保护的存储器地址。 未受保护的存储器地址可以通过外部接口直接访问。
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公开(公告)号：US20140095944A1
公开(公告)日：2014-04-03
申请号：US13631934
申请日：2012-09-29
CPC分类号： G06F1/3253 , Y02D10/151
摘要： An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.
摘要翻译： 公开了一种用于优化在基于处理器的系统内操作的链路的等待时间和功率的装置和方法。 该装置和方法包括内置于不依赖于队列深度阈值的队列中的等待时间计。 该装置和方法还包括反馈逻辑，其优化围绕增加的延迟目标的功率降低以对由链路的物理属性施加的缓慢的重新供应行为作出反应。
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