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1.发明授权公开(公告)号：US08429367B2
公开(公告)日：2013-04-23
申请号：US11965953
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
IPC分类号： G06F1/04
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于时钟使能（CKE）协调的系统，方法和装置。 在一些实施例中，存储器控制器包括用于预测排定的请求是否将被发布到等级的逻辑。 存储器控制器还可以包括用于预测排定的请求是否将不被发布到等级的逻辑。 在一些实施例中，时钟使能（CKE）至少部分地基于预测被断言或取消断言为等级。 描述和要求保护其他实施例。
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2.发明申请公开(公告)号：US20090172681A1
公开(公告)日：2009-07-02
申请号：US11965953
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
IPC分类号： G06F9/46
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于时钟使能（CKE）协调的系统，方法和装置。 在一些实施例中，存储器控制器包括用于预测排定的请求是否将被发布到等级的逻辑。 存储器控制器还可以包括用于预测排定的请求是否将不被发布到等级的逻辑。 在一些实施例中，时钟使能（CKE）至少部分地基于预测被断言或取消断言为等级。 描述和要求保护其他实施例。
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公开(公告)号：US20090171875A1
公开(公告)日：2009-07-02
申请号：US11965955
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
IPC分类号： G06N5/02
CPC分类号： G06N5/02
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于秩协调的系统，方法和装置。 在一些实施例中，主机包括秩协调逻辑。 秩协调逻辑可以包括性能测量逻辑，以至少部分地基于存储器通道的性能来测量存储器通道的性能和停留周期控制逻辑以选择驻留时间的长度。 描述和要求保护其他实施例。
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公开(公告)号：US07885914B2
公开(公告)日：2011-02-08
申请号：US11965955
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
IPC分类号： G06N5/02
CPC分类号： G06N5/02
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于秩协调的系统，方法和装置。 在一些实施例中，主机包括秩协调逻辑。 秩协调逻辑可以包括性能测量逻辑，以至少部分地基于存储器通道的性能来测量存储器通道的性能和停留周期控制逻辑以选择驻留时间的长度。 描述和要求保护其他实施例。
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公开(公告)号：US07991963B2
公开(公告)日：2011-08-02
申请号：US12006326
申请日：2007-12-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor.
摘要翻译： 在一个实施例中，该方法提供从多个处理器的处理器接收对所请求的高速缓存行的存储器访问请求; 通过从其中存储所请求的高速缓存线的存储器页引入来存储与所请求的高速缓存行相关联的一致性信息，所述存储器页面还包括具有与所请求的高速缓存行对应的一致性信息的目录行; 根据一致性信息读取与所请求的高速缓存线相关联的数据; 并将数据返回到处理器。
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公开(公告)号：US20090172295A1
公开(公告)日：2009-07-02
申请号：US12006326
申请日：2007-12-31
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor.
摘要翻译： 在一个实施例中，该方法提供从多个处理器的处理器接收对所请求的高速缓存行的存储器访问请求; 通过从其中存储所请求的高速缓存线的存储器页引入来存储与所请求的高速缓存行相关联的一致性信息，所述存储器页面还包括具有与所请求的高速缓存行对应的一致性信息的目录行; 根据一致性信息读取与所请求的高速缓存线相关联的数据; 并将数据返回到处理器。
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公开(公告)号：US20160147280A1
公开(公告)日：2016-05-26
申请号：US14554585
申请日：2014-11-26
申请人： Tessil Thomas , Lokesh Sharma , Buck W. Gremel , Ian M. Steiner
发明人： Tessil Thomas , Lokesh Sharma , Buck W. Gremel , Ian M. Steiner
CPC分类号： G06F1/206 , G06F1/3243 , Y02D10/152 , Y02D10/16
摘要： In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括执行指令的至少一个核心，与所述至少一个核心相关联的一个或多个热传感器以及耦合到所述至少一个核心的功率控制器。 功率控制器具有用于接收关于处理器的温度信息的控制逻辑，并且至少部分地基于温度信息动态地确定最大允许平均功率限制。 控制逻辑可以进一步保持处理器的静态最大基本操作频率，而不管温度信息的值。 描述和要求保护其他实施例。
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公开(公告)号：US20200310872A1
公开(公告)日：2020-10-01
申请号：US16367581
申请日：2019-03-28
申请人： Krishnamurthy Jambur Sathyanarayana , Robert Valentine , Alexander Gendler , Shmuel Zobel , Gavri Berger , Ian M. Steiner , Nikhil Gupta , Eyal Hadas , Edo Hachamo , Sumesh Subramanian
发明人： Krishnamurthy Jambur Sathyanarayana , Robert Valentine , Alexander Gendler , Shmuel Zobel , Gavri Berger , Ian M. Steiner , Nikhil Gupta , Eyal Hadas , Edo Hachamo , Sumesh Subramanian
IPC分类号： G06F9/48 , G06F9/38 , G06F9/30 , G06F9/4401
摘要： In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.
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公开(公告)号：US09977482B2
公开(公告)日：2018-05-22
申请号：US13992706
申请日：2011-12-21
申请人： Ankush Varma , Ian M. Steiner , Krishnakanth V. Sistla , Matthew M. Bace , Vivek Garg , Martin T. Rowland , Jeffrey S. Wilder
发明人： Ankush Varma , Ian M. Steiner , Krishnakanth V. Sistla , Matthew M. Bace , Vivek Garg , Martin T. Rowland , Jeffrey S. Wilder
CPC分类号： G06F1/324 , G06F13/382
摘要： An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.
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10.发明授权Dynamically modifying a power/performance tradeoff based on processor utilization 有权基于处理器利用率动态修改功率/性能折衷公开(公告)号：US09372524B2
公开(公告)日：2016-06-21
申请号：US13326605
申请日：2011-12-15
申请人： Krishnakanth V. Sistla , Mark Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Daniel Borkowski , Vivek Garg , Cagdas Akturan , Avinash N. Ananthakrishnan
发明人： Krishnakanth V. Sistla , Mark Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Daniel Borkowski , Vivek Garg , Cagdas Akturan , Avinash N. Ananthakrishnan
CPC分类号： G06F9/5094 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有功率控制器的多核处理器，所述功率控制器具有在处理器的利用率超过阈值水平时将功率管理策略从功率偏置策略动态切换到性能偏差策略的逻辑。 因此，在低利用率下，可以实现降低的功率消耗，而在更高的利用率下，可以实现更高的性能。 描述和要求保护其他实施例。
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