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公开(公告)号：US20090171875A1
公开(公告)日：2009-07-02
申请号：US11965955
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
IPC分类号： G06N5/02
CPC分类号： G06N5/02
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于秩协调的系统，方法和装置。 在一些实施例中，主机包括秩协调逻辑。 秩协调逻辑可以包括性能测量逻辑，以至少部分地基于存储器通道的性能来测量存储器通道的性能和停留周期控制逻辑以选择驻留时间的长度。 描述和要求保护其他实施例。
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2.发明授权公开(公告)号：US08429367B2
公开(公告)日：2013-04-23
申请号：US11965953
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
IPC分类号： G06F1/04
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于时钟使能（CKE）协调的系统，方法和装置。 在一些实施例中，存储器控制器包括用于预测排定的请求是否将被发布到等级的逻辑。 存储器控制器还可以包括用于预测排定的请求是否将不被发布到等级的逻辑。 在一些实施例中，时钟使能（CKE）至少部分地基于预测被断言或取消断言为等级。 描述和要求保护其他实施例。
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公开(公告)号：US07885914B2
公开(公告)日：2011-02-08
申请号：US11965955
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
IPC分类号： G06N5/02
CPC分类号： G06N5/02
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于秩协调的系统，方法和装置。 在一些实施例中，主机包括秩协调逻辑。 秩协调逻辑可以包括性能测量逻辑，以至少部分地基于存储器通道的性能来测量存储器通道的性能和停留周期控制逻辑以选择驻留时间的长度。 描述和要求保护其他实施例。
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4.发明申请公开(公告)号：US20090172681A1
公开(公告)日：2009-07-02
申请号：US11965953
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
IPC分类号： G06F9/46
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于时钟使能（CKE）协调的系统，方法和装置。 在一些实施例中，存储器控制器包括用于预测排定的请求是否将被发布到等级的逻辑。 存储器控制器还可以包括用于预测排定的请求是否将不被发布到等级的逻辑。 在一些实施例中，时钟使能（CKE）至少部分地基于预测被断言或取消断言为等级。 描述和要求保护其他实施例。
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公开(公告)号：US20090172442A1
公开(公告)日：2009-07-02
申请号：US11968142
申请日：2007-12-31
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/3225
摘要： Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described.
摘要翻译： 本发明的实施例用多相电压调节器向DRAM或其他存储器件供电。 耦合到多相电压调节器的功率控制器根据预定标准使多相电压调节器的一个或多个相位被激活或去激活（脱落）。 因此，本发明的实施例通过为存储器件提供一个或多个降低的功率状态来改善功率管理。 描述其他实施例。
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公开(公告)号：US07804733B2
公开(公告)日：2010-09-28
申请号：US11968142
申请日：2007-12-31
IPC分类号： G11C7/00
CPC分类号： G06F1/26 , G06F1/3225
摘要： Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described.
摘要翻译： 本发明的实施例用多相电压调节器向DRAM或其他存储器件供电。 耦合到多相电压调节器的功率控制器根据预定标准使多相电压调节器的一个或多个相位被激活或去激活（脱落）。 因此，本发明的实施例通过为存储器件提供一个或多个降低的功率状态来改善功率管理。 描述其他实施例。
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公开(公告)号：US09292465B2
公开(公告)日：2016-03-22
申请号：US13993106
申请日：2011-12-21
申请人： Malay Trivedi , Mohan K. Nair , Joseph Murray , Devadatta V. Bodas , James W. Alexander , Vijayendra K. Hoskoti
发明人： Malay Trivedi , Mohan K. Nair , Joseph Murray , Devadatta V. Bodas , James W. Alexander , Vijayendra K. Hoskoti
CPC分类号： G06F13/42 , G06F13/387 , G06F2213/0026 , Y02D10/14 , Y02D10/151
摘要： Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always active even at very low traffic rates. Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement for integrated and non-integrated ports located downstream for the PCIe controller. This provides power savings with little impact on performance. Other embodiments are discussed herein.
摘要翻译： 实施例帮助动态配置PCIe链路的宽度，并确定如何最佳地配置适当的链路宽度。 这有助于避免PCIe链路几乎总是处于活动状态，即使在非常低的流量速率。 实施例基于例如位于PCIe控制器下游的集成和非集成端口的带宽需求的运行时监视来实现这些益处。 这提供了功率节省，对性能影响不大。 本文讨论了其它实施例。
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公开(公告)号：US20140019654A1
公开(公告)日：2014-01-16
申请号：US13993106
申请日：2011-12-21
申请人： Malay Trivedi , Mohan K. Nair , Joseph Murray , Devadatta V. Bodas , James W. Alexander , Vijayendra K. Hoskoti
发明人： Malay Trivedi , Mohan K. Nair , Joseph Murray , Devadatta V. Bodas , James W. Alexander , Vijayendra K. Hoskoti
IPC分类号： G06F13/42
CPC分类号： G06F13/42 , G06F13/387 , G06F2213/0026 , Y02D10/14 , Y02D10/151
摘要： Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always active even at very low traffic rates. Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement for integrated and non-integrated ports located downstream for the PCIe controller. This provides power savings with little impact on performance. Other embodiments are discussed herein.
摘要翻译： 实施例帮助动态配置PCIe链路的宽度，并确定如何最佳地配置适当的链路宽度。 这有助于避免PCIe链路几乎总是处于活动状态，即使在非常低的流量速率。 实施例基于例如位于PCIe控制器下游的集成和非集成端口的带宽需求的运行时监视来实现这些益处。 这提供了功率节省，对性能影响不大。 本文讨论了其它实施例。
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公开(公告)号：US09280194B2
公开(公告)日：2016-03-08
申请号：US13532743
申请日：2012-06-25
IPC分类号： G06F1/26 , G06F1/32 , G06F13/38 , G06F11/14 , H04L12/40 , G06F11/34 , G06F13/40 , G06F13/16 , H04L12/24 , H04B5/00 , G06F12/08
CPC分类号： G06F1/3262 , G06F1/32 , G06F1/3206 , G06F1/3253 , G06F1/3278 , G06F11/1423 , G06F11/349 , G06F12/0831 , G06F13/1678 , G06F13/38 , G06F13/4018 , G06F13/4027 , G06F2213/0062 , H04B5/0031 , H04L12/4013 , H04L41/0896 , Y02D10/151 , Y02D10/157
摘要： Described herein are embodiments of an apparatus configured for dynamic link width modulation, a system including an apparatus configured for dynamic link width modulation, a method for dynamic link width modulation, and computer-readable media having instructions that, if executed by one or more processors, cause an apparatus to perform a dynamic link width modulation method. An apparatus configured for dynamic link width modulation may include a first counter for determining a length of a queue of packets at a source of a link, a second counter for determining a rate of utilization of the link, and a power control unit configured to modify a width of the link based at least in part on the length of the queue and the rate of utilization. Other embodiments may be described and/or claimed.
摘要翻译： 这里描述的是被配置用于动态链路宽度调制的装置的实施例，包括被配置用于动态链路宽度调制的装置的系统，用于动态链路宽度调制的方法，以及具有指令的计算机可读介质，所述指令如果由一个或多个处理器 使得设备执行动态链路宽度调制方法。 配置用于动态链路宽度调制的装置可以包括用于确定链路源的分组队列的长度的第一计数器，用于确定链路利用率的第二计数器，以及配置为修改链路的功率控制单元 链路的宽度至少部分地基于队列的长度和利用率。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09195404B2
公开(公告)日：2015-11-24
申请号：US14109534
申请日：2013-12-17
申请人： James W. Alexander , Devadatta V. Bodas , Muralidhar Rajappa , Ramkumar Nagappan , Andy Hoffman
发明人： James W. Alexander , Devadatta V. Bodas , Muralidhar Rajappa , Ramkumar Nagappan , Andy Hoffman
CPC分类号： G06F3/065 , G06F3/0614 , G06F3/0622 , G06F3/0673 , G06F12/0223 , G06F12/0804 , G06F12/14 , G06F12/1425 , G06F21/74 , G06F21/79 , G06F2212/1024
摘要： Mechanisms for exposing a protected memory address are provided. A processing device may store a data value at a protected memory address. The protected memory address may be a control register or a status register. The processing device may identify a mirror relationship between the protected memory address and an unprotected memory address and copy the data value from the protected memory address to the unprotected memory address. The unprotected memory address may be directly accessible via an external interface.
摘要翻译： 提供暴露受保护的存储器地址的机制。 处理设备可以将数据值存储在受保护的存储器地址处。 受保护的存储器地址可以是控制寄存器或状态寄存器。 处理设备可以识别受保护的存储器地址和未受保护的存储器地址之间的镜像关系，并将数据值从受保护的存储器地址复制到未受保护的存储器地址。 未受保护的存储器地址可以通过外部接口直接访问。
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