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    Snap hook
    2.
    发明申请
    Snap hook 失效
    扣钩

    公开(公告)号：US20070294867A1

    公开(公告)日：2007-12-27

    申请号：US11474939

    申请日：2006-06-27

    Applicant: Kuan-Yu Lin

    Inventor： Kuan-Yu Lin

    IPC: F16B45/04

    CPC classification number: F16B45/04 ,  Y10T24/45372 ,  Y10T24/45382 ,  Y10T24/45403

    Abstract: A snap hook has a body, a sliding latch, a resilient element, a swivel and a connector. The body has a shaft and a hook. The shaft is tubular and has an upper end and a lower end. The hook is connected to and extends from the upper end of the shaft. A guide slot is defined longitudinally the shaft and communicates with the lower end of the shaft. Accordingly, no sharp edges are formed near the sliding latch so a person opening the snap hook will not be injured. In addition, assembling the snap hook is easy.

    Abstract translation: 卡扣钩具有主体，滑动闩锁，弹性元件，旋转件和连接器。 身体有一个轴和一个钩子。 轴是管状的并且具有上端和下端。 钩连接到轴的上端并从轴的上端延伸。 引导槽纵向地限定轴并与轴的下端连通。 因此，在滑动闩锁附近没有形成锋利的边缘，所以打开卡扣钩的人不会受到伤害。 此外，组装卡扣钩很容易。

    Low power consumption analog-to-digital converter
    3.
    发明授权
    Low power consumption analog-to-digital converter 有权
    低功耗模数转换器

    公开(公告)号：US07817071B2

    公开(公告)日：2010-10-19

    申请号：US12414653

    申请日：2009-03-30

    Applicant: Kuan-Yu Lin ,  Tsung-Shuen Hung

    Inventor： Kuan-Yu Lin ,  Tsung-Shuen Hung

    IPC: H03M1/10

    CPC classification number: H03M1/1004 ,  H03M1/1042 ,  H03M1/162 ,  H03M1/167

    Abstract: A low power consumption analog-to-digital converter (ADC) is provided. The switched capacitor circuit and the operational amplifier of the pipelined stage within the present low power consumption ADC are designed to close loop, and the operational amplifier is operated at the incomplete settling of the linear settling, namely, the operational amplifier is not operated at the slew state. Therefore, the pipelined stage would not produce signal dependent distortion, such that the gain error produced by the operational amplifier could be seen as a constant gain error.

    Abstract translation: 提供了低功耗模数转换器（ADC）。 目前低功耗ADC中的开关电容电路和流水线级的运算放大器设计为闭环，运算放大器在线性稳定的不完全稳定运行，即运算放大器不在 压倒状态 因此，流水线阶段不会产生信号相关的失真，使得由运算放大器产生的增益误差可以被看作是恒定的增益误差。

    LOW POWER CONSUMPTION ANALOG-TO-DIGITAL CONVERTER
    4.
    发明申请
    LOW POWER CONSUMPTION ANALOG-TO-DIGITAL CONVERTER 有权
    低功耗模拟数字转换器

    公开(公告)号：US20100141492A1

    公开(公告)日：2010-06-10

    申请号：US12414653

    申请日：2009-03-30

    Applicant: Kuan-Yu Lin ,  Tsung-Shuen Hung

    Inventor： Kuan-Yu Lin ,  Tsung-Shuen Hung

    IPC: H03M1/10

    CPC classification number: H03M1/1004 ,  H03M1/1042 ,  H03M1/162 ,  H03M1/167

    Abstract: A low power consumption analog-to-digital converter (ADC) is provided. The switched capacitor circuit and the operational amplifier of the pipelined stage within the present low power consumption ADC are designed to close loop, and the operational amplifier is operated at the incomplete settling of the linear settling, namely, the operational amplifier is not operated at the slew state. Therefore, the pipelined stage would not produce signal dependent distortion, such that the gain error produced by the operational amplifier could be seen as a constant gain error.

    Abstract translation: 提供了低功耗模数转换器（ADC）。 目前低功耗ADC中的开关电容电路和流水线级的运算放大器设计为闭环，运算放大器在线性稳定的不完全稳定运行，即运算放大器不在 压倒状态 因此，流水线阶段不会产生信号相关的失真，使得由运算放大器产生的增益误差可以被看作是恒定的增益误差。

    Switched capacitor comparator circuit
    6.
    发明授权
    Switched capacitor comparator circuit 有权
    开关电容比较电路

    公开(公告)号：US09557354B2

    公开(公告)日：2017-01-31

    申请号：US13362576

    申请日：2012-01-31

    Applicant: Chih-Chia Chen ,  Kuan-Yu Lin ,  Chin-Chou Liu

    Inventor： Chih-Chia Chen ,  Kuan-Yu Lin ,  Chin-Chou Liu

    IPC: G01R19/165 ,  H03K5/24 ,  G01R31/3185 ,  G01R31/28

    CPC classification number: G01R19/16552 ,  G01R31/2856 ,  G01R31/318513 ,  H03K5/24

    Abstract: A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal.

    Abstract translation: 包括接收输入参考电压的第一开关，接收输入测试电压的第二开关，第一开关和第二开关的电路并联电连接。 电路还包括与第一开关和第二开关串联电连接的第一电容器。 电路还包括反馈级，其包括与反馈开关并联电连接的反馈反相器，其中反馈级与第一电容器串联电连接。 电路还包括与反馈级串联电连接的第一反相器和与第一反相器串联电连接的第三开关。 电路还包括与第三反相器并联电连接的第二反相器，第二反相器和第三反相器与第三开关串联电连接，并且第三反相器输出第一输出信号。

    METHOD FOR PLACING DECOUPLING CAPACITORS
    10.
    发明申请
    METHOD FOR PLACING DECOUPLING CAPACITORS 有权
    放置电容器的方法

    公开(公告)号：US20140082575A1

    公开(公告)日：2014-03-20

    申请号：US13618519

    申请日：2012-09-14

    Applicant: Chi-Wei Hu ,  Kuan-Yu Lin ,  Wan-Chun Chen ,  Chin-Chou Liu

    Inventor： Chi-Wei Hu ,  Kuan-Yu Lin ,  Wan-Chun Chen ,  Chin-Chou Liu

    IPC: G06F17/50

    CPC classification number: G06F17/5063 ,  G06F17/5081 ,  G06F2217/82

    Abstract: A method comprises selecting a region from a layout pattern of an integrated circuit, wherein the region comprises a plurality of functional units, and wherein the functional units are not coupled to each other through a variety of connection components, identifying hot spots in the region using a first threshold and inserting a plurality of decoupling capacitors adjacent to the hot spots.

    Abstract translation: 一种方法包括从集成电路的布局图案中选择区域，其中该区域包括多个功能单元，并且其中功能单元不通过各种连接部件彼此耦合，使用 第一阈值并且插入与所述热点相邻的多个解耦电容器。

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