公开(公告)号：US06743717B1

公开(公告)日：2004-06-01

申请号：US10397627

申请日：2003-03-26

Applicant: Kuo-Chien Wu ,  Jeng-Ping Lin

Inventor： Kuo-Chien Wu ,  Jeng-Ping Lin

IPC: H01L2144

CPC classification number: H01L21/823425 ,  H01L21/823418 ,  H01L27/105 ,  H01L29/78

Abstract: A method for forming silicide at source and drain. The method includes providing a semiconductor substrate having an active region and peripheral region, wherein gates with source and drain on two sides are formed in the peripheral region, conformally forming a barrier layer to cover the active region and the peripheral region, forming a mask layer to cover the barrier layer at the active region, removing the barrier layer from the peripheral region; removing the mask layer, forming a metal layer to cover the peripheral region, and subjecting the metal layer to thermal process such that silicon reacts with the metal to form silicide at the source and the drain.

Abstract translation: 一种在源极和漏极处形成硅化物的方法。 该方法包括提供具有有源区和周边区域的半导体衬底，其中在周边区域中形成有源极和漏极的栅极，保形地形成阻挡层以覆盖有源区和周边区域，形成掩模层 覆盖有源区的阻挡层，从边缘区域去除阻挡层; 去除掩模层，形成覆盖周边区域的金属层，并对金属层进行热处理，使得硅与金属反应，在源极和漏极处形成硅化物。

公开(公告)号：US20140070359A1

公开(公告)日：2014-03-13

申请号：US13615526

申请日：2012-09-13

Applicant: Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

Inventor： Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

IPC: H01L27/00

CPC classification number: H01L21/3081 ,  H01L21/76224

Abstract: A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.

Abstract translation: 存储器阵列包括由第一和第二STI结构围绕的菱形形状的AA区域。 第一STI结构在菱形AA区域的长边上沿着第一方向延伸并且具有深度d1。 第二STI结构沿着菱形AA区域的较短边沿第二方向延伸，并且具有两个深度：d2和d3，其中d1和d2比d3浅。

公开(公告)号：US07541244B2

公开(公告)日：2009-06-02

申请号：US11491704

申请日：2006-07-24

Applicant: Jeng-Ping Lin ,  Pei-Ing Lee

Inventor： Jeng-Ping Lin ,  Pei-Ing Lee

IPC: H01L21/336

CPC classification number: H01L29/7834 ,  H01L27/10876 ,  H01L29/42368 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

公开(公告)号：US07285377B2

公开(公告)日：2007-10-23

申请号：US10715616

申请日：2003-11-18

Applicant: Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

Inventor： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC: G03F7/00

CPC classification number: H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract translation: 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US06794250B2

公开(公告)日：2004-09-21

申请号：US10449296

申请日：2003-05-29

Applicant: Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

Inventor： Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

IPC: H01L218247

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gaze. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the control gate to serve as source and drain regions with the first doping region.

Abstract translation: 垂直分闸门闪存单元。 存储单元包括衬底，浮置栅极，控制栅极，隧道层，第一掺杂区域和第二掺杂区域。 浮动栅极设置在沟槽的下部，并通过浮栅氧化层与相邻衬底绝缘。 控制栅极设置在浮置栅极上并通过控制栅极氧化物层与相邻衬底绝缘。 栅极间电介质层设置在浮置栅极和控制栅极之间，用于浮动栅极和控制注视的绝缘。 第一掺杂区域形成在与控制栅极相邻的衬底中，并且第二掺杂区域形成在第一掺杂区域下方的衬底中并且与控制栅极相邻，以用作具有第一掺杂区域的源极和漏极区域。

公开(公告)号：US06781181B2

公开(公告)日：2004-08-24

申请号：US10453502

申请日：2003-06-04

Applicant: Kuen-Chy Heo ,  Jeng-Ping Lin

Inventor： Kuen-Chy Heo ,  Jeng-Ping Lin

IPC: H01L27108

CPC classification number: H01L29/945 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10882

Abstract: A DRAM cell with a vertical transistor and a deep trench capacitor. In the DRAM cell, a deep trench capacitor is disposed in a substrate; a gate is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and an upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region. The DRAM cell can be applied to an open bitline DRAM, a folded bitline DRAM, and a folded bitline DRAM with bordless bitline contact window.

Abstract translation: 具有垂直晶体管和深沟槽电容器的DRAM单元。 在DRAM单元中，深沟槽电容器设置在基板中; 栅极设置在深沟槽电容器上; 离子掺杂层设置在电容器的栅极和上电极之间; 绝缘层设置在栅极和离子掺杂层之间; 栅极绝缘层设置在栅极的侧壁上; 沟道区位于衬底的栅极绝缘层的旁边; 源极设置在离子掺杂层的侧壁上并在垂直沟道区的一侧上; 并且在垂直沟道区域的另一侧设置有公共漏极。 DRAM单元可以应用于开放的位线DRAM，折叠位线DRAM和具有无边位线接触窗口的折叠位线DRAM。

公开(公告)号：US06432774B1

公开(公告)日：2002-08-13

申请号：US09854698

申请日：2001-05-15

Applicant: Kuen-Chy Heo ,  Jeng-Ping Lin

Inventor： Kuen-Chy Heo ,  Jeng-Ping Lin

IPC: H01L21336

Abstract: A method of fabricating a vertical transistor of a memory cell is disclosed. According to this method, a semiconductor substrate is first provided. A pad layer is formed over the substrate. Then, a deep trench is formed in the substrate. In the deep trench, a trench capacitor is formed, a collar oxide layer is then formed on the sidewalls above the trench capacitor. A first conductive layer is formed above the trench capacitor. A second conductive layer is formed to fill the deep trench. The pad layer, the substrate, the first and the second conductive layers and the collar oxide layer are patterned. A first insulating layer is deposited to form the Shallow Trench Isolation. Both sides of the Shallow Trench Isolation and a portion of the second conductive layer are removed to form a buried strap and an opening. The pad layer is removed. A second insulating layer is formed over the substrate and the buried strap, and is removed after forming a well. A third insulating layer is formed on the substrate. After removing the third insulating layer on top surface of the substrate, the gate oxide is formed. Sequentially, a third conductive layer and a fourth conductive layer are formed to fill the opening and to cover the substrate. The third and the fourth conductive layers are patterned to form the gate. The source/drain regions and a fourth insulating layer are formed. The fabrication of the vertical transistor of a memory cell is completed.

公开(公告)号：US20110256697A1

公开(公告)日：2011-10-20

申请号：US13171405

申请日：2011-06-28

Applicant: Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

Inventor： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

IPC: H01L21/265

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

Abstract translation: 凹入栅极晶体管器件包括嵌入在半导体衬底中形成的栅极沟槽中的栅电极，其中栅极沟槽包括垂直侧壁和U形底部。 源区域设置在半导体衬底内的栅极沟槽的一侧。 漏极区域设置在其另一侧。 在栅电极和半导体衬底之间形成非对称栅介质层。 不对称栅极介电层在栅电极和漏极区之间具有第一厚度，并且在栅极和源极区之间具有第二厚度，其中第一厚度比第二厚度厚。

公开(公告)号：US07994559B2

公开(公告)日：2011-08-09

申请号：US12167231

申请日：2008-07-02

Applicant: Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

Inventor： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

IPC: H01L21/82

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

Abstract translation: 凹入栅极晶体管器件包括嵌入在半导体衬底中形成的栅极沟槽中的栅电极，其中栅极沟槽包括垂直侧壁和U形底部。 源区域设置在半导体衬底内的栅极沟槽的一侧。 漏极区域设置在其另一侧。 在栅电极和半导体衬底之间形成非对称栅介质层。 不对称栅极介电层在栅电极和漏极区之间具有第一厚度，并且在栅极和源极区之间具有第二厚度，其中第一厚度比第二厚度厚。

公开(公告)号：US20050045936A1

公开(公告)日：2005-03-03

申请号：US10761985

申请日：2004-01-21

Applicant: Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10832 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66181

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.