利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

56 条记录 (耗时 0.025 秒)

    Memory circuits, systems, and method of interleaving accesses thereof
    2.
    发明授权
    Memory circuits, systems, and method of interleaving accesses thereof 有权
    存储器电路，系统及其访问方法

    公开(公告)号：US08164974B2

    公开(公告)日：2012-04-24

    申请号：US12698423

    申请日：2010-02-02

    申请人： Kuoyuan Hsu ,  Ming-Chieh Huang ,  Young Suk Kim ,  Subramani Kengeri

    发明人： Kuoyuan Hsu ,  Ming-Chieh Huang ,  Young Suk Kim ,  Subramani Kengeri

    IPC分类号： G11C11/00

    CPC分类号： G11C7/1042 ,  G11C8/04

    摘要： An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.

    摘要翻译： 交错存储器电路包括具有第一存储单元的第一存储器组。 第一本地控制电路与第一存储体耦合。 第二存储器组包括第二存储器单元。 第二本地控制电路与第二存储体耦合。 IO块与第一存储体和第二存储体耦合。 全局控制电路与第一和第二本地控制电路耦合。 交织接入包括具有第一周期和第二周期的时钟信号，用于分别访问第一存储器单元和第二存储单元，其中第二周期能够使第一本地控制电路触发第一 读取列选择信号RSSL用于访问第一个存储单元。

    Memory circuits, systems, and method of interleavng accesses thereof
    3.
    发明授权
    Memory circuits, systems, and method of interleavng accesses thereof 有权
    存储器电路，系统及其访问方法

    公开(公告)号：US08547779B2

    公开(公告)日：2013-10-01

    申请号：US13429117

    申请日：2012-03-23

    申请人： Kuoyuan Hsu ,  Ming-Chieh Huang ,  Young Suk Kim ,  Subramani Kengeri

    发明人： Kuoyuan Hsu ,  Ming-Chieh Huang ,  Young Suk Kim ,  Subramani Kengeri

    IPC分类号： G11C8/00 ,  G11C8/18

    CPC分类号： G11C7/1042 ,  G11C8/04

    摘要： An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit coupled with the memory bank. The interleaved memory circuit further includes a global control circuit coupled with the local control circuit, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell, where the second cycle is capable of enabling the local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.

    摘要翻译： 交织存储器电路包括一个存储体，该存储体包括至少一个用于存储表示第一数据的电荷的第一存储单元，第一存储单元与第一字线和第一位线耦合。 交错存储器电路还包括与存储体耦合的本地控制电路。 交错存储器电路还包括与本地控制电路耦合的全局控制电路，包括具有用于访问第一存储器单元的第一周期和第二周期的时钟信号的交织访问，其中第二周期能够实现本地控制 触发用于访问第一存储器单元的第一读取列选择信号RSSL的第一转换。

    MEMORY CIRCUITS, SYSTEMS, AND METHOD OF INTERLEAVING ACCESSES THEREOF
    4.
    发明申请
    MEMORY CIRCUITS, SYSTEMS, AND METHOD OF INTERLEAVING ACCESSES THEREOF 有权
    记忆电路，系统及其接入方法

    公开(公告)号：US20100214857A1

    公开(公告)日：2010-08-26

    申请号：US12698423

    申请日：2010-02-02

    申请人： Kuoyuan Hsu ,  Ming-Chieh Huang ,  Young Suk Kim ,  Subramani Kengeri

    发明人： Kuoyuan Hsu ,  Ming-Chieh Huang ,  Young Suk Kim ,  Subramani Kengeri

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1042 ,  G11C8/04

    摘要： An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.

    摘要翻译： 交错存储器电路包括具有第一存储单元的第一存储器组。 第一本地控制电路与第一存储体耦合。 第二存储器组包括第二存储器单元。 第二本地控制电路与第二存储体耦合。 IO块与第一存储体和第二存储体耦合。 全局控制电路与第一和第二本地控制电路耦合。 交织接入包括具有第一周期和第二周期的时钟信号，用于分别访问第一存储器单元和第二存储单元，其中第二周期能够使第一本地控制电路触发第一 读取列选择信号RSSL用于访问第一个存储单元。

    Charge shared match line differential generation for CAM
    8.
    发明授权
    Charge shared match line differential generation for CAM 有权
    为CAM共享匹配线差分生成

    公开(公告)号：US06343029B1

    公开(公告)日：2002-01-29

    申请号：US09782576

    申请日：2001-02-13

    申请人： Subramani Kengeri ,  Steve Lim

    发明人： Subramani Kengeri ,  Steve Lim

    IPC分类号： G11C1500

    CPC分类号： G11C15/00 ,  G11C15/04

    摘要： A content addressable memory (CAM) with built-in power saving management. The CAM includes a comparator circuit region that is coupled to a match line (ML) as well as a swing line (SL). The comparator circuit region is coupled to CAM cells. The comparator region is adapted for comparing match data with stored data within the CAM cells. The ML has its ML voltage level pre-charged to a pre-charge voltage level (Vc). Additionally, the SL is pre-charged to ground. In turn, in response to a data mismatch detected by the comparator, the ML voltage level drops from Vc by a ML voltage swing (Vswing) while the SL charge shares with the Ml. Advantageously, in response to this data mismatch, the SL charge shares with the ML such that Vswing is approximately less or equal to Vc/2. That is, the charge sharing prevents the ML from discharging all the way to ground. Thus, because Vswing is as large as Vc in a conventional CAM whereas Vswing is as large as about Vc/2 in the invention, the invention's Vswing restriction provides significant more power saving.

    摘要翻译： 内容可寻址存储器（CAM），内置省电管理。 CAM包括耦合到匹配线（ML）以及摆动线（SL）的比较器电路区域。 比较器电路区域耦合到CAM单元。 比较器区域适于将匹配数据与CAM单元内的存储数据进行比较。 ML具有预充电到预充电电压电平（Vc）的ML电压电平。 此外，SL预充电到地面。 反过来，响应于比较器检测到的数据不匹配，ML电压电平从Vc下降到ML电压摆幅（Vswing），而SL电荷与M1分配。 有利地，响应于该数据不匹配，SL电荷与ML共享，使得Vswing大致小于或等于Vc / 2。 也就是说，电荷共享防止了ML一路向地面放电。 因此，由于在本发明中Vswing与Vc一样大，而Vswing与Vc / 2一样大，所以本发明的Vswing限制提供了更大的功率节省。

    DRAM based refresh-free ternary CAM
    9.
    发明授权
    DRAM based refresh-free ternary CAM 有权
    基于DRAM的无刷新三元CAM

    公开(公告)号：US06331961B1

    公开(公告)日：2001-12-18

    申请号：US09591033

    申请日：2000-06-09

    申请人： Subramani Kengeri ,  Hemraj K. Hingarh

    发明人： Subramani Kengeri ,  Hemraj K. Hingarh

    IPC分类号： G11C700

    CPC分类号： G11C11/406 ,  G11C15/043

    摘要： A ternary state content addressable memory (CAM) cell that includes two DRAM cells. In addition to a port for controlling and transmitting data to the CAM, another port is exclusively used for refreshing the DRAM cells. A refresh word line is coupled to the two DRAM cells for performing DRAW cell refresh. A refresh bit line is coupled to the first of the two DRAM cells for refreshing this first DRAM cell. A refresh bit line is coupled to the second of the two DRAM cells for refreshing this second DRAM cell. Problematic power consumption and voltage swing found in a conventional CAM are overcome in the CAM. A swing line (SL) is coupled to said first and second DRAM cells and a local match line (LML) of said CAM cell, said SL having an adjustable voltage level for changing voltage swing in said LML to regulate trade-off between power consumption and speed of said CAM cell.

    摘要翻译： 包含两个DRAM单元的三态状态内容可寻址存储器（CAM）单元。 除了用于控制和发送数据到CAM的端口之外，另一个端口专门用于刷新DRAM单元。 刷新字线耦合到两个DRAM单元用于执行DRAW单元刷新。 刷新位线耦合到两个DRAM单元中的第一个用于刷新该第一DRAM单元。 刷新位线耦合到两个DRAM单元中的第二个用于刷新该第二DRAM单元。 在CAM中克服了传统CAM中出现的有问题的功耗和电压摆动。 摆动线（SL）耦合到所述第一和第二DRAM单元和所述CAM单元的局部匹配线（LML），所述SL具有用于改变所述LML中的电压摆幅的可调节电压电平，以调节功率消耗之间的权衡 和所述CAM单元的速度。

    Interleaved stitch using segmented word lines
    10.
    发明授权
    Interleaved stitch using segmented word lines 有权
    使用分段字线的交错针迹

    公开(公告)号：US6141236A

    公开(公告)日：2000-10-31

    申请号：US266175

    申请日：1999-03-10

    申请人： Subramani Kengeri

    发明人： Subramani Kengeri

    IPC分类号： G11C8/14 ,  G11C11/408 ,  G11C11/4097 ,  G11C5/06

    CPC分类号： G11C8/14 ,  G11C11/408 ,  G11C11/4097

    摘要： A word line stitch mechanism to be used in high-density DRAMs is presented herein. The word line stitch mechanism of the present invention eliminates the problem caused by using the conventional word line stitch methods of the prior art in the high-density DRAMs. In the present invention, the word lines are segmented with an space between the two adjacent word line segments. Thereafter, the contacts between the word line segments and the associated metal layers are established such that the contact overlap areas are completely adjacent to all or a portion of the spaces between the word line segments of the adjacent word lines.

    摘要翻译： 本文提出了用于高密度DRAM的字线缝合机构。 本发明的字线缝合机构消除了在高密度DRAM中使用现有技术的常规字线缝合方法所引起的问题。 在本发明中，字线被划分成两个相邻字线段之间的空间。 此后，字线段和相关联的金属层之间的接触被建立成使得接触重叠区域完全邻近相邻字线的字线段之间的空间的全部或一部分。