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    SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM
    1.
    发明申请
    SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM 有权
    具有穿过底部的自制障碍层的半导体器件

    公开(公告)号：US20140097538A1

    公开(公告)日：2014-04-10

    申请号：US13648433

    申请日：2012-10-10

    申请人： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

    发明人： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

    IPC分类号： H01L21/768 ,  H01L23/48

    CPC分类号： H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

    摘要翻译： 提供了一种用于形成半导体器件的方法。 通常，通过在金属层上设置金属层，覆盖层和覆盖层上的超低k层来形成器件。 然后通过超低k层和盖层形成通孔。 一旦形成通孔，就可以选择性地将阻挡层（例如，钴（Co），钽（Ta），钴 - 钨 - 磷化物（CoWP）或能够充当铜（CU）扩散阻挡层的其它金属） 通孔的底面。 然后将衬垫层（例如锰（MN）或铝（AL））施加到通孔的一组侧壁。 然后可以用随后的金属层（具有或不具有种子层）填充通孔，然后可以进一步处理（例如，退火）该器件。

    METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES BY FORMING A COPPER-BASED SEED LAYER HAVING AN AS-DEPOSITED THICKNESS PROFILE AND THEREAFTER PERFORMING AN ETCHING PROCESS AND ELECTROLESS COPPER DEPOSITION
    2.
    发明申请
    METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES BY FORMING A COPPER-BASED SEED LAYER HAVING AN AS-DEPOSITED THICKNESS PROFILE AND THEREAFTER PERFORMING AN ETCHING PROCESS AND ELECTROLESS COPPER DEPOSITION 有权
    通过形成具有沉积厚度剖面的铜基层和形成蚀刻过程和电沉积铜沉积的形成铜基导电结构的方法

    公开(公告)号：US20130309863A1

    公开(公告)日：2013-11-21

    申请号：US13476692

    申请日：2012-05-21

    申请人： Sean X. Lin ,  Ming He ,  Xunyuan Zhang ,  Larry Zhao

    发明人： Sean X. Lin ,  Ming He ,  Xunyuan Zhang ,  Larry Zhao

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76874 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76879

    摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating material, performing a deposition process to form an as-deposited copper-based seed layer above the layer of insulating material in the trench/via, wherein the copper-based seed layer has a first portion that is positioned above a bottom of the trench/via that is thicker than second portions of the copper seed layer that are positioned above sidewalls of the trench/via, performing an etching process on the as-deposited copper-based seed layer to substantially remove portions of the second portions of the as-deposited copper-based seed layer and performing an electroless deposition process to fill the trench/via with a copper-based material.

    摘要翻译： 这里公开了在集成电路器件上形成铜基导电结构的各种方法。 在一个示例中，该方法包括在绝缘材料层中形成沟槽/通孔，执行沉积工艺以在沟槽/通孔中的绝缘材料层上形成沉积的基于铜的种子层，其中铜 - 基于晶种的层具有位于沟槽/通孔的底部之上的第一部分，其比位于沟槽/通孔侧壁上方的铜籽晶层的第二部分更厚，对沉积的铜进行蚀刻工艺 基本种子层，以基本上去除沉积的铜基种子层的第二部分的部分，并执行无电沉积工艺以用铜基材料填充沟槽/通孔。

    Methods of forming copper-based conductive structures on an integrated circuit device
    3.
    发明授权
    Methods of forming copper-based conductive structures on an integrated circuit device 有权
    在集成电路器件上形成铜基导电结构的方法

    公开(公告)号：US08517769B1

    公开(公告)日：2013-08-27

    申请号：US13422295

    申请日：2012-03-16

    申请人： Sean X. Lin ,  Ming He ,  Xunyuan Zhang ,  Larry Zhao

    发明人： Sean X. Lin ,  Ming He ,  Xunyuan Zhang ,  Larry Zhao

    IPC分类号： H01L21/4763 ,  H01L21/00

    CPC分类号： H01L21/76879 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76865 ,  H01L21/76874 ,  H01L2924/0002

    摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes the steps of forming a trench/via in a layer of insulating material, forming a copper-based seed layer above the layer of insulating material and in the trench/via, performing a heating process on the copper-based seed layer to increase an amount of the copper-based seed layer positioned proximate a bottom of the trench/via, performing an etching process on said copper-based seed layer and performing an electroless copper deposition process to fill the trench/via with a copper-based material.

    摘要翻译： 这里公开了在集成电路器件上形成铜基导电结构的各种方法。 在一个示例中，该方法包括以下步骤：在绝缘材料层中形成沟槽/通孔，在绝缘材料层上方和沟槽/通孔中形成铜基种子层，在铜 - 以增加位于沟槽/通孔的底部附近的铜基种子层的量，对所述铜基种子层进行蚀刻工艺，并执行无电镀铜沉积工艺以填充沟槽/通孔 铜基材料。

    Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper deposition
    4.
    发明授权
    Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper deposition 有权
    通过形成具有沉积厚度分布的铜基种子层，然后进行蚀刻工艺和无电镀铜沉积形成铜基导电结构的方法

    公开(公告)号：US08673766B2

    公开(公告)日：2014-03-18

    申请号：US13476692

    申请日：2012-05-21

    申请人： Sean X. Lin ,  Ming He ,  Xunyuan Zhang ,  Larry Zhao

    发明人： Sean X. Lin ,  Ming He ,  Xunyuan Zhang ,  Larry Zhao

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76874 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76879

    摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating material, performing a deposition process to form an as-deposited copper-based seed layer above the layer of insulating material in the trench/via, wherein the copper-based seed layer has a first portion that is positioned above a bottom of the trench/via that is thicker than second portions of the copper seed layer that are positioned above sidewalls of the trench/via, performing an etching process on the as-deposited copper-based seed layer to substantially remove portions of the second portions of the as-deposited copper-based seed layer and performing an electroless deposition process to fill the trench/via with a copper-based material.

    摘要翻译： 这里公开了在集成电路器件上形成铜基导电结构的各种方法。 在一个示例中，该方法包括在绝缘材料层中形成沟槽/通孔，执行沉积工艺以在沟槽/通孔中的绝缘材料层上方形成沉积的基于铜的种子层，其中铜 - 基于晶种的层具有位于沟槽/通孔的底部之上的第一部分，其比位于沟槽/通孔侧壁上方的铜籽晶层的第二部分更厚，对沉积的铜进行蚀刻工艺 基本种子层，以基本上去除沉积的铜基种子层的第二部分的部分，并执行无电沉积工艺以用铜基材料填充沟槽/通孔。

    Cu capping layer deposition with improved integrated circuit reliability
    6.
    发明授权
    Cu capping layer deposition with improved integrated circuit reliability 失效
    Cu覆盖层沉积具有改进的集成电路可靠性

    公开(公告)号：US06897144B1

    公开(公告)日：2005-05-24

    申请号：US10100915

    申请日：2002-03-20

    申请人： Minh Van Ngo ,  Paul Raymond Besser ,  Larry Zhao

    发明人： Minh Van Ngo ,  Paul Raymond Besser ,  Larry Zhao

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76834 ,  H01L21/76877

    摘要： The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu using dual frequency powers, holding the high frequency power constant and controlling the compressive stress of the deposited silicon nitride capping layer by varying the low frequency power to the susceptor, thereby enabling reduction of the compressive stress below about 2×107 Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH3 diluted with N2, and then depositing the silicon nitride capping layer by plasma enhanced chemical vapor deposition, while varying the low frequency power between about 100 to about 300 watts. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

    摘要翻译： 通过控制氮化物沉积条件以减小沉积的氮化物层的压应力，从而减少沿着Cu-氮化物界面的扩散，显着改善了氮化物覆盖的Cu线的电迁移电阻。 实施例包括使用双频功率在镶嵌Cu上沉积氮化硅覆盖层，保持高频功率恒定，并通过改变对基座的低频功率来控制沉积的氮化硅覆盖层的压缩应力，从而能够降低压缩 压力低于约2×10 7帕斯卡。 实施例还包括用含N 2 N 3稀释的含有NH 3的软质等离子体连续地并且连续地处理暴露的在内的Cu的平坦化表面，然后沉积氮化硅覆盖层 通过等离子体增强化学气相沉积，同时改变约100至约300瓦特之间的低频功率。 实施例还包括形成在介电常数（k）小于约3.9的电介质材料中的Cu双镶嵌结构。

    Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface
    7.
    发明授权
    Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface 有权
    沿Cu /氮化物界面形成具有减少的电迁移的氮化物封盖的Cu线的方法

    公开(公告)号：US06429128B1

    公开(公告)日：2002-08-06

    申请号：US09902587

    申请日：2001-07-12

    申请人： Paul Raymond Besser ,  Minh Van Ngo ,  Larry Zhao

    发明人： Paul Raymond Besser ,  Minh Van Ngo ,  Larry Zhao

    IPC分类号： H01L2144

    CPC分类号： H01L21/76862 ,  H01L21/3185 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu at a reduced RF power, e.g., about 400 to about 500 watts and an increased spacing, e.g., about 680 to about 720 mils, to reduce the compressive stress of the deposited silicon nitride layer to below about 2×107 Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH3 diluted with N2, ramping up the introduction of SiH4 and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure and N2 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

    摘要翻译： 通过控制氮化物沉积条件以减小沉积的氮化物层的压应力，从而减少沿着Cu-氮化物界面的扩散，显着改善了氮化物覆盖的Cu线的电迁移电阻。 实施例包括以降低的RF功率（例如，约400至约500瓦特）和增加的间隔（例如，约680至约720密耳）在镶嵌的Cu上沉积氮化硅覆盖层，以减小沉积的氮化硅层的压应力 低于约2×107帕斯卡。 实施例还包括用包含用N 2稀释的NH 3的软质等离子体连续和连续地处理嵌入的Cu的暴露的平坦化表面，使引入SiH4升高，然后启动氮化硅覆盖层的等离子体增强化学气相沉积，同时保持基本上 在等离子体处理期间，相同的压力和N2的流速，SiH4斜坡上升和氮化硅沉积。 实施例还包括形成在介电常数（k）小于约3.9的电介质材料中的Cu双镶嵌结构。

    Method of selectively alloying interconnect regions by deposition process
    8.
    发明授权
    Method of selectively alloying interconnect regions by deposition process 有权
    通过沉积工艺选择合金化互连区域的方法

    公开(公告)号：US06656834B1

    公开(公告)日：2003-12-02

    申请号：US09884027

    申请日：2001-06-20

    申请人： Paul R. Besser ,  Larry Zhao

    发明人： Paul R. Besser ,  Larry Zhao

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/76864 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in the underlying metal. Once the copper fill is performed in the via, an annealing step allows the alloying element to go into solid solution with the copper in and around the via. The solid solution of the alloying element and copper at the bottom of the via in the copper line improves the electromigration reliability of the structure.

    摘要翻译： 金属互连结构及其制造方法提供了在电介质层中对通孔进行排列的合金元素层。 因此，合金元素层被插入临界电迁移破坏部位，即位于底层金属的通孔下方的快速扩散部位。 一旦在通孔中进行铜填充，退火步骤允许合金元素进入固体溶液，铜通过其中和周围。 铜线中通孔底部的合金元素和铜的固溶体提高了结构的电迁移可靠性。

    Dielectric barrier layer for a copper metallization layer having a varying silicon concentration along its thickness
    9.
    发明授权
    Dielectric barrier layer for a copper metallization layer having a varying silicon concentration along its thickness 失效
    用于铜金属化层的介电阻挡层，沿其厚度具有不同的硅浓度

    公开(公告)号：US07381660B2

    公开(公告)日：2008-06-03

    申请号：US10717122

    申请日：2003-11-19

    申请人： Larry Zhao ,  Jeremy Martin ,  Hartmut Ruelke

    发明人： Larry Zhao ,  Jeremy Martin ,  Hartmut Ruelke

    IPC分类号： H01L21/44 ,  H01L21/31

    CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834

    摘要： A silicon nitride layer having a silicon-rich sub-layer and a standard sub-layer is formed on a copper surface to obtain excellent electromigration characteristics due to the standard sub-layer that is in contact with the copper, while maintaining a superior diffusion barrier behavior due to the silicon-rich sub-layer. By combining these sub-layers, the overall thickness of the silicon nitride layer may be kept small compared to conventional silicon nitride barrier layers, thereby reducing the capacitive coupling of adjacent copper lines.

    摘要翻译： 在铜表面上形成具有富硅亚层和标准子层的氮化硅层，由于与铜接触的标准子层而具有良好的电迁移特性，同时保持优异的扩散阻挡层 由于富含硅的子层而产生的行为。 通过组合这些子层，与常规氮化硅阻挡层相比，氮化硅层的总体厚度可以保持较小，从而减小了相邻铜线的电容耦合。

    Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices
    10.
    发明授权
    Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices 有权
    阻挡金属层反向电镀以提高铜互连器件的电迁移性能

    公开(公告)号：US06261963B1

    公开(公告)日：2001-07-17

    申请号：US09611729

    申请日：2000-07-07

    申请人： Larry Zhao ,  Paul R. Besser ,  Eric M. Apelgren ,  Christian Zistl ,  Jonathan B. Smith

    发明人： Larry Zhao ,  Paul R. Besser ,  Eric M. Apelgren ,  Christian Zistl ,  Jonathan B. Smith

    IPC分类号： H01L21302

    CPC分类号： H01L21/76873 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  Y10S438/927

    摘要： A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.

    摘要翻译： 提供了一种用于形成导电互连的方法，所述方法包括在结构层上形成第一介电层，在第一介电层中形成第一开口，并在第一开口中形成第一导电结构。 该方法还包括在第一介电层之上和第一导电结构之上形成第二电介质层，在第二导电结构的至少一部分上方的第二电介质层中形成第二开口，第二开口具有侧表面和 并且在侧表面和底表面上的第二开口中形成至少一个阻挡金属层。 此外，该方法包括从底表面去除至少一个阻挡金属层的一部分，以及在第二开口中形成第二导电结构，第二导电结构与第一导电结构的至少一部分接触。 该方法还包括通过使第二导电结构和第一导电结构退火来形成导电互连。