公开(公告)号：US07267880B2

公开(公告)日：2007-09-11

申请号：US10866936

申请日：2004-06-14

申请人： Leah Miller ,  Annette Krisko ,  Klaus Hartig ,  Roger O'Shaughnessy ,  Gary Pfaff

发明人： Leah Miller ,  Annette Krisko ,  Klaus Hartig ,  Roger O'Shaughnessy ,  Gary Pfaff

IPC分类号： B32B17/06

CPC分类号： C03C17/34 ,  C03C17/3417 ,  C03C17/3423 ,  C03C2218/355 ,  C23C14/0005 ,  Y10T428/24802

摘要： A substrate having a surface carrying a removable transparent film that can be removed by the surface by a desired washing process, and removable presence indicator associated with the removable transparent film, the presence indicator being removable by the same desired washing process as the removable transparent film. A method of producing a substrate having a presence indicator in contact with a removable transparent film a method of washing a substrate having a presence indicator in contact with a removable transparent film are also disclosed.

摘要翻译： 具有表面的基底，其具有可移除的透明膜，其可以通过所需的洗涤过程被表面除去，以及与可移除的透明膜相关联的可移除存在指示器，该存在指示器可通过与可移除的透明膜相同的所需洗涤过程来移除 。 还公开了一种制造具有与可去除的透明膜接触的存在指示器的基板的方法，其中洗涤具有与可移除透明膜接触的存在指示器的基板的方法。

公开(公告)号：US20060223341A1

公开(公告)日：2006-10-05

申请号：US11097895

申请日：2005-04-01

申请人： Arun Ramakrishnan ,  Farshad Ghahghahi ,  Aritharan Thurairajaratnam ,  Leah Miller

发明人： Arun Ramakrishnan ,  Farshad Ghahghahi ,  Aritharan Thurairajaratnam ,  Leah Miller

IPC分类号： H05K1/00

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10734 ,  H01L2924/00

摘要： A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern. Substantially all of the contacts are disposed at a standard pitch one from another on a single contact surface.

摘要翻译： 包括设置在图案的第一部分中的高速发射器触点的接触图案，其中高速发射器接触设置在发射机差分对中。 高速接收器触点设置在图案的第二部分中，其中图案的第一部分不与图案的第二部分分散，并且高速接收器触点设置在接收器差分对中。 在图案的第一部分和图案的第二部分之间设置至少一条其他触点的一条直线，其他触点不包含任何高速发送器触点和高速接收器触点。 低速IO触点设置在图案的第三部分中，其中图案的第三部分相对于图案的第一部分和图案的第二部分布置在图案的内部。 基本上所有的触点在单个接触表面上彼此之间以标准间距设置。

公开(公告)号：US20070023930A1

公开(公告)日：2007-02-01

申请号：US11193808

申请日：2005-07-29

申请人： Leah Miller ,  Gregory Winn

发明人： Leah Miller ,  Gregory Winn

IPC分类号： H01L23/48

CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/15173 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0245 ,  H05K1/112 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/10674

摘要： The embodiments of the present invention are directed toward the design of routing patterns, including elements such as contacts, traces, and vias, for high speed differential signal pairs in integrated circuit package substrates.

摘要翻译： 本发明的实施例涉及布线图案的设计，包括用于集成电路封装基板中的高速差分信号对的诸如触点，迹线和通孔的元件。

公开(公告)号：US20060202303A1

公开(公告)日：2006-09-14

申请号：US11078052

申请日：2005-03-11

申请人： Leah Miller ,  Ivor Barber ,  Aritharan Thurairajaratnam

发明人： Leah Miller ,  Ivor Barber ,  Aritharan Thurairajaratnam

IPC分类号： H01L29/00

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/162 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/09309 ,  H01L2924/00

摘要： The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

公开(公告)号：US07829424B2

公开(公告)日：2010-11-09

申请号：US12174479

申请日：2008-07-16

申请人： Leah Miller ,  Ivor Barber ,  Aritharan Thurairajaratnam

发明人： Leah Miller ,  Ivor Barber ,  Aritharan Thurairajaratnam

IPC分类号： H01L21/20

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/162 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/09309 ,  H01L2924/00

摘要： The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

摘要翻译： 本发明涉及一种制造具有去耦电容器的集成电路封装的方法，所述去耦电容器使用构想为不使用去耦电容器的封装设计。 该封装通过对原始设计的最小重新设计实现，而不需要重新设计信号迹线图案。 本发明涉及用通孔带替换顶部和底部接合焊盘，然后用具有与下面的通孔带电连接的导电通孔的介电层覆盖顶部和底部参考平面。 然后在电介质层上形成具有与下面参考平面相反极性的平面。 这些平面包括与通孔对准的焊盘阵列。 去耦电容器安装到封装的顶部，并与封装顶部的平面和紧靠的下面的参考平面电连接，而不通过与封装的信号平面通过的电容器的电连接。

公开(公告)号：US20050093173A1

公开(公告)日：2005-05-05

申请号：US10702996

申请日：2003-11-05

申请人： Leah Miller ,  Aritharan Thurairajaratnam

发明人： Leah Miller ,  Aritharan Thurairajaratnam

IPC分类号： H01L23/498 ,  H01L25/16 ,  H01L23/48

CPC分类号： H01L23/49838 ,  H01L25/16 ,  H01L2224/16 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3025

摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.

摘要翻译： 本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。 衬底还包括至少一个具有形成在其上的多个电信号迹线的信号层。 该封装包括安装在封装上的分立的非有源电气部件，使得集成电路管芯通过离散的非有源电气部件与封装的电信号迹线电连接。 并且在一个特定实施方案中，分立的非有源电子部件包括串联布置在电信号迹线和裸片之间的电容元件，使得电容器作为封装安装的AC耦合电容器工作。

公开(公告)号：US07791210B2

公开(公告)日：2010-09-07

申请号：US10702996

申请日：2003-11-05

申请人： Leah Miller ,  Aritharan Thurairajaratnam

发明人： Leah Miller ,  Aritharan Thurairajaratnam

IPC分类号： H01L23/48

CPC分类号： H01L23/49838 ,  H01L25/16 ,  H01L2224/16 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3025

摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.

摘要翻译： 本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。 衬底还包括至少一个具有形成在其上的多个电信号迹线的信号层。 该封装包括安装在封装上的分立的非有源电气部件，使得集成电路管芯通过离散的非有源电气部件与封装的电信号迹线电连接。 并且在一个特定实施方案中，分立的非有源电子部件包括串联布置在电信号迹线和裸片之间的电容元件，使得电容器作为封装安装的AC耦合电容器工作。

公开(公告)号：US07508062B2

公开(公告)日：2009-03-24

申请号：US11078052

申请日：2005-03-11

申请人： Leah Miller ,  Ivor Barber ,  Aritharan Thurairajaratnam

发明人： Leah Miller ,  Ivor Barber ,  Aritharan Thurairajaratnam

IPC分类号： H01L23/053 ,  H01L23/12

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/162 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/09309 ,  H01L2924/00

摘要： The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

摘要翻译： 本发明涉及一种制造具有去耦电容器的集成电路封装的方法，所述去耦电容器使用构想为不使用去耦电容器的封装设计。 该封装通过对原始设计的最小重新设计实现，而不需要重新设计信号迹线图案。 本发明涉及用通孔带替换顶部和底部接合焊盘，然后用具有与下面的通孔带电连接的导电通孔的介电层覆盖顶部和底部参考平面。 然后在电介质层上形成具有与下面参考平面相反极性的平面。 这些平面包括与通孔对准的焊盘阵列。 去耦电容器安装到封装的顶部，并与封装顶部的平面和紧靠的下面的参考平面电连接，而不通过与封装的信号平面通过的电容器的电连接。

公开(公告)号：US20070114644A1

公开(公告)日：2007-05-24

申请号：US11283340

申请日：2005-11-18

申请人： Leah Miller ,  Jeffrey Hall

发明人： Leah Miller ,  Jeffrey Hall

IPC分类号： H01L23/02

CPC分类号： H01L23/49816 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A family of package substrates adapted to receive a family of integrated circuits having different sizes and provide electrical connections between the integrated circuits and a circuit board. Each package substrate in the family includes a package substrate having a die side and a circuit board side. The package substrate has a size that is consistent for all of the package substrates in the family of package substrates. The die side has integrated circuit contacts disposed in a pattern designed to make electrical connections to a given integrated circuit in the family of integrated circuits for which the package substrate is designed, as defined by locations of contacts on the given integrated circuit. The circuit board side has circuit board contacts disposed in a pattern and with functional assignments that are consistent for all of the package substrates in the family of package substrates.

摘要翻译： 一组封装衬底，适于接收具有不同尺寸的集成电路系列，并提供集成电路和电路板之间的电连接。 家族中的每个封装衬底包括具有管芯侧和电路板侧的封装衬底。 封装衬底的尺寸对于封装衬底系列中的所有封装衬底是一致的。 模具侧具有集成电路触点，其设计成图案，其被设计成与集成电路系列中的给定集成电路进行电连接，集成电路系列由集成电路设计，如由给定集成电路上的触点位置所限定。 电路板侧具有以图案布置的电路板触点，并且具有与封装衬底系列中的所有封装衬底一致的功能分配。