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公开(公告)号：US20060202303A1
公开(公告)日：2006-09-14
申请号：US11078052
申请日：2005-03-11
IPC分类号： H01L29/00
CPC分类号： H01L23/49822 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H05K1/0231 , H05K1/112 , H05K1/162 , H05K3/4644 , H05K3/4688 , H05K2201/09309 , H01L2924/00
摘要： The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.
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2.发明授权公开(公告)号：US07829424B2
公开(公告)日：2010-11-09
申请号：US12174479
申请日：2008-07-16
IPC分类号： H01L21/20
CPC分类号： H01L23/49822 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H05K1/0231 , H05K1/112 , H05K1/162 , H05K3/4644 , H05K3/4688 , H05K2201/09309 , H01L2924/00
摘要： The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.
摘要翻译： 本发明涉及一种制造具有去耦电容器的集成电路封装的方法，所述去耦电容器使用构想为不使用去耦电容器的封装设计。 该封装通过对原始设计的最小重新设计实现，而不需要重新设计信号迹线图案。 本发明涉及用通孔带替换顶部和底部接合焊盘，然后用具有与下面的通孔带电连接的导电通孔的介电层覆盖顶部和底部参考平面。 然后在电介质层上形成具有与下面参考平面相反极性的平面。 这些平面包括与通孔对准的焊盘阵列。 去耦电容器安装到封装的顶部，并与封装顶部的平面和紧靠的下面的参考平面电连接，而不通过与封装的信号平面通过的电容器的电连接。
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3.发明授权公开(公告)号：US07508062B2
公开(公告)日：2009-03-24
申请号：US11078052
申请日：2005-03-11
IPC分类号： H01L23/053 , H01L23/12
CPC分类号： H01L23/49822 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H05K1/0231 , H05K1/112 , H05K1/162 , H05K3/4644 , H05K3/4688 , H05K2201/09309 , H01L2924/00
摘要： The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.
摘要翻译： 本发明涉及一种制造具有去耦电容器的集成电路封装的方法，所述去耦电容器使用构想为不使用去耦电容器的封装设计。 该封装通过对原始设计的最小重新设计实现，而不需要重新设计信号迹线图案。 本发明涉及用通孔带替换顶部和底部接合焊盘，然后用具有与下面的通孔带电连接的导电通孔的介电层覆盖顶部和底部参考平面。 然后在电介质层上形成具有与下面参考平面相反极性的平面。 这些平面包括与通孔对准的焊盘阵列。 去耦电容器安装到封装的顶部，并与封装顶部的平面和紧靠的下面的参考平面电连接，而不通过与封装的信号平面通过的电容器的电连接。
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公开(公告)号：US20060223341A1
公开(公告)日：2006-10-05
申请号：US11097895
申请日：2005-04-01
IPC分类号： H05K1/00
CPC分类号： H01L23/49838 , H01L23/49816 , H01L23/66 , H01L2223/6638 , H01L2924/0002 , H01L2924/15311 , H05K1/112 , H05K2201/09227 , H05K2201/09236 , H05K2201/10734 , H01L2924/00
摘要： A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern. Substantially all of the contacts are disposed at a standard pitch one from another on a single contact surface.
摘要翻译： 包括设置在图案的第一部分中的高速发射器触点的接触图案，其中高速发射器接触设置在发射机差分对中。 高速接收器触点设置在图案的第二部分中，其中图案的第一部分不与图案的第二部分分散，并且高速接收器触点设置在接收器差分对中。 在图案的第一部分和图案的第二部分之间设置至少一条其他触点的一条直线，其他触点不包含任何高速发送器触点和高速接收器触点。 低速IO触点设置在图案的第三部分中，其中图案的第三部分相对于图案的第一部分和图案的第二部分布置在图案的内部。 基本上所有的触点在单个接触表面上彼此之间以标准间距设置。
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5.发明申请Semiconductor package having dicrete non-active electrical components incorporated into the package 有权具有并入到封装中的具有混合非有源电子元件的半导体封装公开(公告)号：US20050093173A1
公开(公告)日：2005-05-05
申请号：US10702996
申请日：2003-11-05
IPC分类号： H01L23/498 , H01L25/16 , H01L23/48
CPC分类号： H01L23/49838 , H01L25/16 , H01L2224/16 , H01L2924/15173 , H01L2924/15311 , H01L2924/19105 , H01L2924/3025
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.
摘要翻译： 本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。 衬底还包括至少一个具有形成在其上的多个电信号迹线的信号层。 该封装包括安装在封装上的分立的非有源电气部件，使得集成电路管芯通过离散的非有源电气部件与封装的电信号迹线电连接。 并且在一个特定实施方案中，分立的非有源电子部件包括串联布置在电信号迹线和裸片之间的电容元件，使得电容器作为封装安装的AC耦合电容器工作。
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6.发明授权Semiconductor package having discrete non-active electrical components incorporated into the package 有权半导体封装具有并入封装中的离散非有源电气元件公开(公告)号：US07791210B2
公开(公告)日：2010-09-07
申请号：US10702996
申请日：2003-11-05
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , H01L25/16 , H01L2224/16 , H01L2924/15173 , H01L2924/15311 , H01L2924/19105 , H01L2924/3025
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.
摘要翻译： 本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。 衬底还包括至少一个具有形成在其上的多个电信号迹线的信号层。 该封装包括安装在封装上的分立的非有源电气部件，使得集成电路管芯通过离散的非有源电气部件与封装的电信号迹线电连接。 并且在一个特定实施方案中，分立的非有源电子部件包括串联布置在电信号迹线和裸片之间的电容元件，使得电容器作为封装安装的AC耦合电容器工作。
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公开(公告)号：US07081672B1
公开(公告)日：2006-07-25
申请号：US11073802
申请日：2005-03-07
IPC分类号： H01L23/34
CPC分类号： H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H05K1/0219 , H05K1/0222 , H05K1/0254 , H05K1/0263 , H05K1/0366 , H05K1/115 , H05K3/4602 , H05K2201/029 , H05K2201/09536 , H05K2201/09609 , H01L2924/00 , H01L2224/0401
摘要： A substrate is provided, which has a pattern of voltage supply vias extending through at least a portion of the substrate. Each of a plurality of the voltage supply vias is surrounded by four of the voltage supply vias of a same polarity in four orthogonal directions and by four voltage supply vias of an opposite polarity in four diagonal directions.
摘要翻译： 提供了一种衬底，其具有延伸通过衬底的至少一部分的电压供给通孔的图案。 多个电压供给通路中的每一个由四个正交方向上的相同极性的四个电压供给通孔和四个对角线方向上具有相反极性的四个电压供给通路围绕。
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8.发明授权Measurement of package interconnect impedance using tester and supporting tester 失效使用测试仪和支持测试仪测量封装互连阻抗公开(公告)号：US06946866B2
公开(公告)日：2005-09-20
申请号：US10620057
申请日：2003-07-15
CPC分类号： G01R31/2886
摘要： A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i.e., package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.
摘要翻译： 来自测试仪的测试仪头用于安装探针卡。 DUT /负载板具有被配置为保持衬底的插座。 探针卡的探头引脚与基板上的凸点焊盘接触。 来自DUT /负载板的信号线馈送到测试仪，测试仪连接到具有快速上升时间信号头的DSO。 在测试期间，使用DSO将信号发射到连接到测试头的同轴电缆。 发射信号和反射信号由DSO捕获，然后送入测试仪。 使用该数据，后处理软件用于获得被测器件（即，封装）的互连阻抗与时间的关系。 该方法和设备可以与倒装芯片和线接合产品一起使用。
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公开(公告)号：US06825554B2
公开(公告)日：2004-11-30
申请号：US10387261
申请日：2003-03-11
IPC分类号： H01L2304
CPC分类号： H01L23/49816 , H01L23/49838 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A method for fabricating a semiconductor package having a 2-layer substrate, which includes an array of solder balls, is disclosed. The method includes patterning signal traces on a top layer of the substrate and identifying groups of signal traces to isolate. According to the present invention, a grounded isolation trace is then patterned adjacent to one of the groups of traces to isolate the signal traces, thereby providing noise shielding. In a preferred embodiment, the grounded isolation trace is provided with multiple vias, rather than only one. In a further aspect of the present invention a row of solder balls is connected together and to ground to create a bottom-layer isolating ground trace to further reduce noise. The bottom-layer isolating ground trace may be connected to the top-layer isolating ground trace using a via.
摘要翻译： 公开了一种制造具有包括焊球阵列的2层基板的半导体封装的方法。 该方法包括在衬底的顶层上构图信号迹线，并识别要隔离的信号迹线组。 根据本发明，然后将接地隔离迹线图案化为与所述一组迹线相邻以隔离信号迹线，从而提供噪声屏蔽。 在优选实施例中，接地隔离迹线设置有多个通孔，而不是只有一个。 在本发明的另一方面，一排焊球连接在一起并接地以产生底层隔离接地迹线，以进一步降低噪声。 底层隔离接地迹线可以使用通孔连接到顶层隔离接地迹线。
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公开(公告)号：US06459049B1
公开(公告)日：2002-10-01
申请号：US09885299
申请日：2001-06-20
IPC分类号： H01R909
CPC分类号： H05K1/0216 , H01R31/06 , H05K1/112 , H05K1/117 , H05K2201/09236 , H05K2201/09281 , H05K2201/09727
摘要： A structure for receiving electrical signals near a central portion of the structure and distributing the electrical signals to a peripheral portion of the structure. The structure has a first set of contacts arranged in an array near the central portion of the structure. Electrically conductive traces connect the first set of contacts to a second set of contacts, where each of the electrically conductive traces has at least a first segment, a second segment, and a third segment. The first segment of each of the electrically conductive traces has relatively narrow width and spacing. The first segment of each of the electrically conductive traces is connected on a first end of the first segment to one of the first set of contacts and on a second end of the first segment to the second segment of each of the electrically conductive traces. The second segment of each of the electrically conductive traces has relatively intermediate width and spacing. The second segment of each of the electrically conductive traces is connected on a first end of the second segment to the second end of the first segment and on a second end of the second segment to the third segment of each of the electrically conductive traces. The third segment of each of the electrically conductive traces has relatively wide width and spacing. The third segment of each of the electrically conductive traces is connected on a first end of the third segment to the second end of the second segment and on a second end of the third segment to one of the second set of contacts.
摘要翻译： 一种用于在所述结构的中心部分附近接收电信号并将所述电信号分配到所述结构的外围部分的结构。 该结构具有靠近结构的中心部分排列成阵列的第一组触点。 导电迹线将第一组触点连接到第二组触点，其中每个导电迹线具有至少第一段，第二段和第三段。 每个导电迹线的第一段具有相对较窄的宽度和间隔。 每个导电迹线的第一段在第一段的第一端连接到第一组触点中的一个，并且在第一段的第二端连接到每个导电迹线的第二段。 每个导电迹线的第二段具有相对中间的宽度和间隔。 每个导电迹线的第二段在第二段的第一端连接到第一段的第二端，并且在第二段的第二端连接到每个导电迹线的第三段。 每个导电迹线的第三段具有相对宽的宽度和间隔。 每个导电迹线的第三段在第三段的第一端连接到第二段的第二端，并且在第三段的第二端连接到第二组接触中的一个。
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