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公开(公告)号：US20080164512A1
公开(公告)日：2008-07-10
申请号：US11620075
申请日：2007-01-05
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L21/84 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/1203 , H01L27/15 , H01L29/66825 , H01L29/788
摘要： A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.
摘要翻译： 半导体器件具有半导体衬底，其又具有顶部半导体层部分和顶部半导体层部分下方的主要支撑部分。 互连层在半导体层之上。 存储器阵列位于顶部半导体层部分和互连层的一部分中。 通过去除主要支撑部分的至少一部分并且在移除步骤之后，从与互连层相对的一侧将光施加到存储器阵列来擦除存储器。 结果是存储器阵列从背面接收光并被擦除。
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2.发明授权Method of making a phase change memory cell having a silicide heater in conjunction with a FinFET 有权制造具有与FinFET结合的硅化物加热器的相变存储单元的方法公开(公告)号：US08563355B2
公开(公告)日：2013-10-22
申请号：US12016739
申请日：2008-01-18
IPC分类号： H01L21/06
CPC分类号： H01L27/2436 , H01L29/785 , H01L45/06 , H01L45/1226 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A phase change memory (PCM) cell includes a transistor, a PCM structure, and a heater. The transistor has a first current electrode and a second current electrode in a structure, and a channel region having a first portion along a first sidewall of the structure and having a second portion along a second sidewall of the structure. The second sidewall is opposite the first sidewall. The transistor has a control electrode that has a first portion adjacent to the first sidewall and a second portion adjacent to the second sidewall. The PCM structure exhibits first and second resistive values when in first and second phase states, respectively. The heater is on the structure and produces heat when current flows through the heater for changing the phase state of the phase change structure.
摘要翻译： 相变存储器（PCM）单元包括晶体管，PCM结构和加热器。 晶体管具有结构中的第一电流电极和第二电流电极，以及具有沿着结构的第一侧壁的第一部分并且具有沿着结构的第二侧壁的第二部分的沟道区域。 第二侧壁与第一侧壁相对。 晶体管具有控制电极，该控制电极具有与第一侧壁相邻的第一部分和与第二侧壁相邻的第二部分。 当分别处于第一和第二相位状态时，PCM结构呈现出第一和第二电阻值。 当电流流过加热器以改变相变结构的相位状态时，加热器在结构上并产生热量。
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公开(公告)号：US07820491B2
公开(公告)日：2010-10-26
申请号：US11620075
申请日：2007-01-05
CPC分类号： H01L27/105 , H01L21/84 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/1203 , H01L27/15 , H01L29/66825 , H01L29/788
摘要： A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.
摘要翻译： 半导体器件具有半导体衬底，其又具有顶部半导体层部分和顶部半导体层部分下方的主要支撑部分。 互连层在半导体层之上。 存储器阵列位于顶部半导体层部分和互连层的一部分中。 通过去除主要支撑部分的至少一部分并且在移除步骤之后，从与互连层相对的一侧将光施加到存储器阵列来擦除存储器。 结果是存储器阵列从背面接收光并被擦除。
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公开(公告)号：US20090184306A1
公开(公告)日：2009-07-23
申请号：US12016739
申请日：2008-01-18
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L29/785 , H01L45/06 , H01L45/1226 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A phase change memory (PCM) cell includes a transistor, a PCM structure, and a heater. The transistor has a first current electrode and a second current electrode in a structure, and a channel region having a first portion along a first sidewall of the structure and having a second portion along a second sidewall of the structure. The second sidewall is opposite the first sidewall. The transistor has a control electrode that has a first portion adjacent to the first sidewall and a second portion adjacent to the second sidewall. The PCM structure exhibits first and second resistive values when in first and second phase states, respectively. The heater is on the structure and produces heat when current flows through the heater for changing the phase state of the phase change structure.
摘要翻译： 相变存储器（PCM）单元包括晶体管，PCM结构和加热器。 晶体管具有结构中的第一电流电极和第二电流电极，以及具有沿着结构的第一侧壁的第一部分并且具有沿着结构的第二侧壁的第二部分的沟道区域。 第二侧壁与第一侧壁相对。 晶体管具有控制电极，该控制电极具有与第一侧壁相邻的第一部分和与第二侧壁相邻的第二部分。 当分别处于第一和第二相状态时，PCM结构呈现出第一和第二电阻值。 当电流流过加热器以改变相变结构的相位状态时，加热器在结构上并产生热量。
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公开(公告)号：US07241695B2
公开(公告)日：2007-07-10
申请号：US11244516
申请日：2005-10-06
IPC分类号： H01L21/302
CPC分类号： H01L29/42368 , B82Y10/00 , H01L21/28273 , H01L21/32139 , H01L28/91 , H01L29/512 , H01L29/513
摘要： A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal. In one embodiment, the pillars are formed from polysilicon and function as the charge storage region of a non-volatile memory cell having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor having an increased capacitance without increasing the surface area of an integrated circuit.
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6.发明授权Process of forming an electronic device including a control gate electrode, a semiconductor layer, and a select gate electrode 有权形成包括控制栅电极，半导体层和选择栅电极的电子器件的工艺公开(公告)号：US08803217B2
公开(公告)日：2014-08-12
申请号：US11685297
申请日：2007-03-13
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42344 , H01L29/42348 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： An electronic device including a nonvolatile memory cell can include a substrate including a first portion and a second portion, wherein a first major surface within the first portion lies at an elevation lower than a second major surface within the second portion. The electronic device can also include a charge storage stack overlying the first portion, wherein the charge storage stack includes discontinuous storage elements. The electronic device can further include a control gate electrode overlying the first portion, and a select gate electrode overlying the second portion, wherein the select gate electrode includes a sidewall spacer. In a particular embodiment, a process can be used to form the charge storage stack and control gate electrode. A semiconductor layer can be formed after the charge storage stack and control gate electrode are formed to achieve the substrate with different major surfaces at different elevations. The select gate electrode can be formed over the semiconductor layer.
摘要翻译： 包括非易失性存储单元的电子设备可以包括包括第一部分和第二部分的基板，其中第一部分内的第一主表面位于比第二部分内的第二主表面低的高度处。 电子设备还可以包括覆盖第一部分的电荷存储堆叠，其中电荷存储堆叠包括不连续的存储元件。 电子器件还可以包括覆盖第一部分的控制栅电极和覆盖第二部分的选择栅电极，其中选择栅电极包括侧壁间隔物。 在特定实施例中，可以使用一种工艺来形成电荷存储堆和控制栅电极。 在形成电荷存储堆和控制栅电极之后可以形成半导体层，以在不同的高度实现具有不同主表面的衬底。 选择栅电极可以形成在半导体层上。
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公开(公告)号：US08097873B2
公开(公告)日：2012-01-17
申请号：US12881678
申请日：2010-09-14
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.
摘要翻译： 相变存储单元具有第一电极，多个柱和第二电极。 多个柱与第一电极电耦合。 每个支柱包括相变材料部分和加热器材料部分。 第二电极电耦合到每个支柱。 在一些示例中，支柱具有小于20纳米的宽度。
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公开(公告)号：US07800164B2
公开(公告)日：2010-09-21
申请号：US12397849
申请日：2009-03-04
IPC分类号： H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译： 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。
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公开(公告)号：US07416945B1
公开(公告)日：2008-08-26
申请号：US11676403
申请日：2007-02-19
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Matthew T. Herrick , Narayanan C. Ramani , Robert F. Steimle
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Matthew T. Herrick , Narayanan C. Ramani , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521
摘要： A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.
摘要翻译： 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中除去在牺牲隔离物上形成的纳米团簇并保留其他纳米团簇。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。
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10.发明申请METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING HIGH VOLTAGE TRANSISTORS, NON-VOLATILE MEMORY TRANSISTORS, AND LOGIC TRANSISTORS 有权制造具有高电压晶体管的半导体器件，非易失性存储器晶体管和逻辑晶体管的方法公开(公告)号：US20080179658A1
公开(公告)日：2008-07-31
申请号：US11627725
申请日：2007-01-26
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/823462 , H01L27/11526 , H01L27/11546 , H01L29/7887
摘要： A semiconductor device is made on a semiconductor substrate. A first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate. After the first insulating layer is formed, a second insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a non-volatile memory transistor in a second region of the substrate. After the second insulating layer is formed, a third insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a logic transistor in a third region of the substrate.
摘要翻译： 在半导体衬底上制造半导体器件。 第一绝缘层形成在半导体衬底上，用作半导体衬底的第一区域中的高电压晶体管的栅极电介质。 在形成第一绝缘层之后，在半导体衬底上形成第二绝缘层，用作在衬底的第二区域中用作非易失性存储晶体管的栅极电介质。 在形成第二绝缘层之后，在半导体衬底上形成第三绝缘层，用作衬底的第三区域中用于逻辑晶体管的栅极电介质。
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