公开(公告)号：US08987055B2

公开(公告)日：2015-03-24

申请号：US14233461

申请日：2011-10-21

申请人： Li Zhang ,  Zhiming Lai ,  Dong Chen ,  Jinhui Chen

发明人： Li Zhang ,  Zhiming Lai ,  Dong Chen ,  Jinhui Chen

IPC分类号： H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49582 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/95 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/03334 ,  H01L2224/0382 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

摘要： Provided is a method for packaging a low-k chip, comprising: attaching onto a carrier wafer a layer of temporary strippable film; arranging inversely a chip (2-1) onto the carrier wafer via the temporary strippable film; attaching thin film layer I (2-4) onto the carrier wafer for packaging; bonding a support wafer (2-5) onto the thin film layer I (2-4) and solidifying; forming a reconstructed wafer consisting of the chip (2-1), thin film layer I (2-4), and the support wafer; detaching the reconstructed wafer from the carrier wafer; completing a rewired metal wiring (2-6) on thin film layer I (2-4); forming a metal column (2-7) at an end of the rewired metal wiring (2-6); attaching thin film layer II (2-8) onto a surface of the metal column (2-7), packaging, and solidifying; coating a metal layer (2-9) on the top of the metal column (2-7), forming BGA solder balls (2-10) on the metal layer (2-9) by means of printing or ball planting; and finally slicing into individual BGA packages the reconstructed wafer having formed the BGA solder balls (2-10).

摘要翻译： 提供了一种用于封装低k芯片的方法，包括：将一层临时剥离膜附着在载体晶片上; 通过临时可剥离膜将芯片（2-1）反向布置在载体晶片上; 将薄膜层I（2-4）附着在载体晶片上进行包装; 将支撑晶片（2-5）接合到薄膜层I（2-4）上并固化; 形成由芯片（2-1），薄膜层I（2-4）和支撑晶片组成的重构晶片; 将重建的晶片从载体晶片分离; 在薄膜层I（2-4）上完成重新布线的金属布线（2-6）; 在重新布线的金属布线（2-6）的一端形成金属柱（2-7）; 将薄膜层II（2-8）附着到金属柱（2-7）的表面上，包装和固化; 在金属柱（2-7）的顶部涂覆金属层（2-9），通过印刷或球面种植在金属层（2-9）上形成BGA焊球（2-10）; 最后将形成BGA焊球（2-10）的重构晶片切割成单独的BGA封装。

公开(公告)号：US20140162404A1

公开(公告)日：2014-06-12

申请号：US14233461

申请日：2011-10-21

申请人： Li Zhang ,  Zhiming Lai ,  Dong Chen ,  Jinhui Chen

发明人： Li Zhang ,  Zhiming Lai ,  Dong Chen ,  Jinhui Chen

IPC分类号： H01L23/00

CPC分类号： H01L23/49582 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/95 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/03334 ,  H01L2224/0382 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

摘要： Provided is a method for packaging a low-k chip, comprising: attaching onto a carrier wafer a layer of temporary strippable film; arranging inversely a chip (2-1) onto the carrier wafer via the temporary strippable film; attaching thin film layer I (2-4) onto the carrier wafer for packaging; bonding a support wafer (2-5) onto the thin film layer I (2-4) and solidifying; forming a reconstructed wafer consisting of the chip (2-1), thin film layer I (2-4), and the support wafer; detaching the reconstructed wafer from the carrier wafer; completing a rewired metal wiring (2-6) on thin film layer I (2-4); forming a metal column (2-7) at an end of the rewired metal wiring (2-6); attaching thin film layer II (2-8) onto a surface of the metal column (2-7), packaging, and solidifying; coating a metal layer (2-9) on the top of the metal column (2-7), forming BGA solder balls (2-10) on the metal layer (2-9) by means of printing or ball planting; and finally slicing into individual BGA packages the reconstructed wafer having formed the BGA solder balls (2-10).

摘要翻译： 提供了一种用于封装低k芯片的方法，包括：将一层临时剥离膜附着在载体晶片上; 通过临时可剥离膜将芯片（2-1）反向布置在载体晶片上; 将薄膜层I（2-4）附着在载体晶片上进行包装; 将支撑晶片（2-5）接合到薄膜层I（2-4）上并固化; 形成由芯片（2-1），薄膜层I（2-4）和支撑晶片组成的重构晶片; 将重建的晶片从载体晶片分离; 在薄膜层I（2-4）上完成重新布线的金属布线（2-6）; 在重新布线的金属布线（2-6）的一端形成金属柱（2-7）; 将薄膜层II（2-8）附着到金属柱（2-7）的表面上，包装和固化; 在金属柱（2-7）的顶部涂覆金属层（2-9），通过印刷或球面种植在金属层（2-9）上形成BGA焊球（2-10）; 最后将形成BGA焊球（2-10）的重构晶片切割成单独的BGA封装。

公开(公告)号：US20140191379A1

公开(公告)日：2014-07-10

申请号：US14233596

申请日：2011-10-21

申请人： Li Zhang ,  Zhiming Lai ,  Dong Chen ,  Jinhui Chen

发明人： Li Zhang ,  Zhiming Lai ,  Dong Chen ,  Jinhui Chen

IPC分类号： H01L23/495

CPC分类号： H01L23/49582 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/95 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/03334 ,  H01L2224/0382 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

摘要： A low-k chip packaging structure comprising chip body I (2-1), a chip electrode (2-2), and a chip surface passivation layer (2-3). Chip body I (2-1) has coated thereon thin film layer I (2-3). Thin film layer I (2-3) has arranged on a rear face thereof a support wafer (2-5). A chip electrode (2-2) is transferred to thin film layer I (2-4) around the exterior of the chip via a rewired metal wiring (2-6). The rewired metal wiring (2-6) has arranged at an end thereof a metal column (2-7). The metal column (2-7) has coated thereon thin film layer II (2-8). The top of the metal column protrudes thin film layer II (2-8). The protruding top of the metal column (2-7) has arranged thereon a metal layer (2-9). The metal layer (2-9) has arranged thereon soldering balls (2-10). The low-k chip packaging structure solves the problem of invalid low-k chip due to concentration of stress during chip packaging process and allows for reduced packaging costs and great product reliability.

摘要翻译： 包括芯体I（2-1），芯片电极（2-2）和芯片表面钝化层（2-3）的低k芯片封装结构。 芯体I（2-1）上涂上薄膜层I（2-3）。 薄膜层I（2-3）在其背面设置有支撑晶片（2-5）。 芯片电极（2-2）通过重新布线的金属布线（2-6）转移到芯片外部的薄膜层I（2-4）上。 重新布线的金属布线（2-6）的一端设有金属柱（2-7）。 金属柱（2-7）上涂有薄膜层II（2-8）。 金属柱的顶部突出薄膜层II（2-8）。 金属柱（2-7）的突出顶部上布置有金属层（2-9）。 金属层（2-9）上布置有焊球（2-10）。 低k芯片封装结构解决了芯片封装过程中由于应力集中引起的无效低k芯片的问题，可以降低封装成本，提高产品可靠性。

公开(公告)号：US09943560B2

公开(公告)日：2018-04-17

申请号：US13577276

申请日：2011-01-26

申请人： James Zhou ,  Dong Chen

发明人： James Zhou ,  Dong Chen

IPC分类号： A61K36/00 ,  A61K36/484 ,  A61K31/404 ,  A61K31/513 ,  A61K33/24 ,  A61K36/815 ,  A61K45/06 ,  A61K31/12

CPC分类号： A61K36/484 ,  A61K31/12 ,  A61K31/404 ,  A61K31/513 ,  A61K33/24 ,  A61K36/815 ,  A61K45/06 ,  A61K2300/00

摘要： The invention provides drug compositions with synergistic effects, which includes alcohol-soluble and water-insoluble liquorices extracts and at least one kind of anti-tumor or glucose-and-lipid-lowering drug/eatable substance, and can be used to treat tumor or lower blood glucose and lipid. Besides, the invention also provides pharmaceutical preparation, pharmaceutical application, therapeutic and preparation methods, etc. related to this drug compositon.

公开(公告)号：US09779106B2

公开(公告)日：2017-10-03

申请号：US14239186

申请日：2012-08-14

申请人： Wei Xu ,  Qiming Deng ,  Dong Chen ,  Sheng Wang ,  Shiguang Huang ,  Qing Liu ,  Yanxia Chen

发明人： Wei Xu ,  Qiming Deng ,  Dong Chen ,  Sheng Wang ,  Shiguang Huang ,  Qing Liu ,  Yanxia Chen

IPC分类号： G06F17/30 ,  G06F9/44 ,  G06F9/445

CPC分类号： G06F17/30174 ,  G06F8/61 ,  G06F9/452

摘要： Disclosed are an application management method and device, applied to a first device connected to a second device. The method includes mapping at least one application in the second device, to obtain at least one corresponding application identifier; detecting a first operation; when the first operation satisfies a first preset condition, determining an application identifier of a first application according to the at least one application identifier; detecting a second operation; when the second operation satisfies a second preset condition, obtaining a corresponding application management command according to the second operation; and sending the application management command to the second device, so that the second device manages the first application according to the application management command.

公开(公告)号：US09657321B2

公开(公告)日：2017-05-23

申请号：US14613128

申请日：2015-02-03

申请人： Jon Y. Takemoto ,  Dong Chen

发明人： Jon Y. Takemoto ,  Dong Chen

IPC分类号： C12N15/52 ,  C12P17/16 ,  C12N9/02 ,  C12N15/70

CPC分类号： C12P17/165 ,  C12N9/0083 ,  C12N15/70 ,  C12Y114/99003

摘要： Methods for producing biliverdin in a microorganism, methods for producing biliverdin from a non-animal source, cells for producing biliverdin and methods for producing cells for producing biliverdin are disclosed.

公开(公告)号：US09250477B2

公开(公告)日：2016-02-02

申请号：US13524144

申请日：2012-06-15

申请人： Dong Chen ,  Xue Dong ,  Cheng Li

发明人： Dong Chen ,  Xue Dong ,  Cheng Li

IPC分类号： G02F1/1337 ,  G02F1/1343

CPC分类号： G02F1/133707 ,  G02F1/134309 ,  G02F2001/134381

摘要： An embodiment of the present disclosure provides an array substrate, and the array substrate including: at least a data line and at least a gate line; and a plurality of pixel units defined by the data line and the gate line. Each of the plurality of pixel units includes a thin film transistor, a first electrode and a second electrode, and the first electrode and the second electrode overlap each other and are insulated from each other and the second electrode is positioned above the first electrode. An alignment film is formed on a surface of the array substrate, a direction of the second electrode and one side of the array substrate form a predetermined angle and a rubbing direction of the alignment film is parallel to the one side of the array substrate.

摘要翻译： 本公开的实施例提供阵列基板，并且阵列基板包括：至少数据线和至少栅极线; 以及由数据线和栅极线限定的多个像素单元。 多个像素单元中的每一个包括薄膜晶体管，第一电极和第二电极，并且第一电极和第二电极彼此重叠并且彼此绝缘，并且第二电极位于第一电极的上方。 在阵列基板的表面上形成取向膜，第二电极的方向和阵列基板的一侧形成预定的角度，并且取向膜的摩擦方向平行于阵列基板的一侧。

公开(公告)号：US09137098B2

公开(公告)日：2015-09-15

申请号：US13584300

申请日：2012-08-13

申请人： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

发明人： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

IPC分类号： H04L12/715 ,  H04L12/24

CPC分类号： H04L41/0663 ,  H04L41/12 ,  H04L41/145 ,  H04L45/04

摘要： According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.

摘要翻译： 根据本发明的一个实施例，提供了一种为节点组网格构建网络通信的方法，所述网格包括M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N 大于1，其中每个节点包括路由器。 该方法包括通过组内链路将每个节点组中的每个节点直接连接到节点组中的每个其他节点，并将M维网格的每个节点组中的每个节点直接连接到M维中的每个相邻节点组中的节点 网格通过组间链接。

公开(公告)号：US09069035B2

公开(公告)日：2015-06-30

申请号：US13333433

申请日：2011-12-21

申请人： Dong Chen

发明人： Dong Chen

IPC分类号： G06F19/00 ,  G01R27/00 ,  G01R31/26 ,  H05B31/00 ,  F21V8/00 ,  F21Y103/00 ,  G01R31/265

CPC分类号： G01R31/2648 ,  F21V29/83 ,  F21V2200/00 ,  F21Y2103/00 ,  G01R31/2656 ,  H05B31/00 ,  H05B2206/00

摘要： A diode model and conductive-probe measurements taken at the wafer lever are used to predict the characterization parameters of a semiconductor device manufactured from the wafer. A current-voltage curve (I-V) model that expresses a current-voltage relationship as a function of resistance, ideality factor, and reverse saturation current is fitted to a number of conductive-probe measurement data. The current-voltage curve (I-Vd) for the device is then estimated by subtracting from the (I-V) model the product of current times the resistance produced by fitting the (I-V) model.

摘要翻译： 使用在晶圆杠杆处获取的二极管模型和导电探针测量来预测从晶片制造的半导体器件的表征参数。 表示作为电阻，理想因子和反向饱和电流的函数的电流 - 电压关系的电流 - 电压曲线（I-V）模型拟合到多个导电探针测量数据。 然后通过从（I-V）模型中减去当前乘积乘以（I-V）模型产生的电阻的乘积，来估计器件的电流 - 电压曲线（I-Vd）。

公开(公告)号：US20150147789A1

公开(公告)日：2015-05-28

申请号：US14613128

申请日：2015-02-03

申请人： Jon Y. Takemoto ,  Dong Chen

发明人： Jon Y. Takemoto ,  Dong Chen

IPC分类号： C12P17/16 ,  C12N9/02

CPC分类号： C12P17/165 ,  C12N9/0083 ,  C12N15/70 ,  C12Y114/99003

摘要： Methods for producing biliverdin in a microorganism, methods for producing biliverdin from a non-animal source, cells for producing biliverdin and methods for producing cells for producing biliverdin are disclosed.

摘要翻译： 公开了一种微生物中生成胆色素的方法，从非动物来源产生胆色素的方法，用于产生胆色素的细胞和用于产生胆色素的细胞的制备方法。