公开(公告)号：US07390753B2

公开(公告)日：2008-06-24

申请号：US11274109

申请日：2005-11-14

申请人： Li-Te Lin ,  Yui Wang ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Li-Te Lin ,  Yui Wang ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/302

CPC分类号： G03F7/40 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.

摘要翻译： 公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。 该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层， 在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。 优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

公开(公告)号：US20070111110A1

公开(公告)日：2007-05-17

申请号：US11274109

申请日：2005-11-14

申请人： Li-Te Lin ,  Yui Wang ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Li-Te Lin ,  Yui Wang ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： G03F1/00 ,  C03C15/00 ,  G03C5/00

CPC分类号： G03F7/40 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.

摘要翻译： 公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。 该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层， 在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。 优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

公开(公告)号：US06503848B1

公开(公告)日：2003-01-07

申请号：US09989804

申请日：2001-11-20

申请人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Huan-Just Lin ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Huan-Just Lin ,  Hun-Jan Tao

IPC分类号： H01L21469

CPC分类号： H01L21/32115 ,  H01L21/31055 ,  H01L21/3127 ,  H01L21/32137

摘要： A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.

摘要翻译： 公开了一种用于平滑多晶硅层的顶表面的方法，由于多晶硅颗粒的形成，沉积的多晶硅层具有粗糙的顶表面。 使用化学气相沉积法沉积聚合物，如CxFyBrz。 聚合物层的厚度足够大，使得聚合物的顶表面至少在多晶硅层顶表面上的晶粒峰值之上的临界距离。 然后使用以相同蚀刻速率蚀刻聚合物和多晶硅的回蚀法蚀刻掉聚合物层和多晶硅层的一部分。 这导致一层多晶硅在整个多晶硅层上具有平滑的顶表面和相同的厚度。

公开(公告)号：US06333271B1

公开(公告)日：2001-12-25

申请号：US09821559

申请日：2001-03-29

申请人： Yuan Hung Chiu ,  Yu-I Wang ,  Hun-Jan Tao ,  Huan Just Lin

发明人： Yuan Hung Chiu ,  Yu-I Wang ,  Hun-Jan Tao ,  Huan Just Lin

IPC分类号： H01L21461

CPC分类号： H01J37/32935 ,  H01J37/32963 ,  H01J2237/3341

摘要： A plasma etch method for plasma etch processing a microelectronic layer formed over a substrate, comprises a two step plasma etch method. Within a first step, the microelectronic layer is etched while employing a first plasma etch method employing a first detection apparatus optimized to measure a thickness of the microelectronic layer. The first detection apparatus controls the first plasma etch method to stop prior to reaching the substrate to thus form from the microelectronic layer a partially etched microelectronic layer. Within a second step, the partially etched microelectronic layer is etched while employing a second plasma etch method employing a second detection apparatus optimized to detect the substrate. The second detection apparatus controls the second etch method to stop on the substrate when etching the partially etched microelectronic layer to form a completely etched microelectronic layer. The method is particularly useful for forming gate electrodes for use within field effect transistors for use within semiconductor integrated circuit microelectronic fabrications.

摘要翻译： 用于等离子体蚀刻处理在衬底上形成的微电子层的等离子体蚀刻方法包括两步等离子体蚀刻方法。 在第一步骤中，使用采用优化以测量微电子层的厚度的第一检测装置的第一等离子体蚀刻方法来蚀刻微电子层。 第一检测装置控制第一等离子体蚀刻方法在到达衬底之前停止，从而从微电子层形成部分蚀刻的微电子层。 在第二步骤中，蚀刻部分蚀刻的微电子层，同时采用采用优化以检测衬底的第二检测装置的第二等离子体蚀刻方法。 当蚀刻部分蚀刻的微电子层以形成完全蚀刻的微电子层时，第二检测装置控制第二蚀刻方法停止在基板上。 该方法特别适用于形成在半导体集成电路微电子制造中使用的场效应晶体管内使用的栅电极。

公开(公告)号：US20050092348A1

公开(公告)日：2005-05-05

申请号：US10701708

申请日：2003-11-05

申请人： Ju-Chien Chiang ,  Ming-Huan Tsai ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Ju-Chien Chiang ,  Ming-Huan Tsai ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： B08B3/08 ,  B08B3/12 ,  C11D3/39 ,  C11D7/08 ,  C11D11/00 ,  H01L21/306 ,  H01L21/311

CPC分类号： H01L21/02052 ,  B08B3/08 ,  B08B3/12 ,  C11D3/3947 ,  C11D7/08 ,  C11D11/0047 ,  H01L21/31122

摘要： The present invention provides aqueous compositions for cleaning integrated circuit substrates. Specifically, in the cleaning of an integrated circuit substrate, disclosed is a method for removing the by-products of the high-k dielectric dry etch process from the integrated circuit substrate, the method including: contacting the integrated circuit substrate with an aqueous composition including an amount, effective for the purpose of a (a) hydrogen fluoride, followed by (b) a mixture of hydrogen peroxide with a compound selected from the group consisting of ammonium hydroxide, hydrochloric acid and sulfuric acid.

摘要翻译： 本发明提供用于清洁集成电路基板的水性组合物。 具体地，在集成电路基板的清洗中，公开了从集成电路基板除去高介电常数干蚀刻工艺的副产物的方法，该方法包括：使集成电路基板与水性组合物接触，所述水性组合物包括 （a）氟化氢，其次是（b）过氧化氢与选自氢氧化铵，盐酸和硫酸的化合物的混合物的量。

公开(公告)号：US06407002B1

公开(公告)日：2002-06-18

申请号：US09636583

申请日：2000-08-10

申请人： Li-Te Lin ,  Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao

发明人： Li-Te Lin ,  Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao

IPC分类号： H01L21302

CPC分类号： H01L21/31144 ,  H01L21/31138 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76877

摘要： A method is provided for improving the tungsten, W-filling of hole openings in semiconductor substrates. This is accomplished by forming an opening—which can be used either as a contact or via hole—with a faceted entrance along with tapered side-walls. This combination of faceted entrance and tapered side-walls improves substantially the tungsten W-filling of contact/via holes in substrates without the formation of key-holes, thereby resulting in metal plugs of high electrical integrity and high reliability.

摘要翻译： 提供了一种提高半导体衬底中的开孔的钨，W填充的方法。 这可以通过形成开口来实现，该开口可以作为接触或通孔使用，与开口的入口以及锥形侧壁一起使用。 面形入口和锥形侧壁的这种组合基本上改善了衬底中的接触/通孔的钨W填充，而没有形成键孔，从而导致高电气完整性和高可靠性的金属插头。

公开(公告)号：US20050118755A1

公开(公告)日：2005-06-02

申请号：US10999270

申请日：2004-11-29

申请人： Li-Te Lin ,  Fang-Chen Cheng ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Li-Te Lin ,  Fang-Chen Cheng ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L29/40

CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139

摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.

摘要翻译： 在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。 在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。 使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。 使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

公开(公告)号：US07109085B2

公开(公告)日：2006-09-19

申请号：US11033912

申请日：2005-01-11

申请人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/336

CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/823828

摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

摘要翻译： 一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

公开(公告)号：US20060154487A1

公开(公告)日：2006-07-13

申请号：US11033912

申请日：2005-01-11

申请人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/8234 ,  H01L21/302

CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/823828

摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

摘要翻译： 一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

公开(公告)号：US20060205224A1

公开(公告)日：2006-09-14

申请号：US11318934

申请日：2005-12-27

申请人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.