公开(公告)号：US06333271B1

公开(公告)日：2001-12-25

申请号：US09821559

申请日：2001-03-29

申请人： Yuan Hung Chiu ,  Yu-I Wang ,  Hun-Jan Tao ,  Huan Just Lin

发明人： Yuan Hung Chiu ,  Yu-I Wang ,  Hun-Jan Tao ,  Huan Just Lin

IPC分类号： H01L21461

CPC分类号： H01J37/32935 ,  H01J37/32963 ,  H01J2237/3341

摘要： A plasma etch method for plasma etch processing a microelectronic layer formed over a substrate, comprises a two step plasma etch method. Within a first step, the microelectronic layer is etched while employing a first plasma etch method employing a first detection apparatus optimized to measure a thickness of the microelectronic layer. The first detection apparatus controls the first plasma etch method to stop prior to reaching the substrate to thus form from the microelectronic layer a partially etched microelectronic layer. Within a second step, the partially etched microelectronic layer is etched while employing a second plasma etch method employing a second detection apparatus optimized to detect the substrate. The second detection apparatus controls the second etch method to stop on the substrate when etching the partially etched microelectronic layer to form a completely etched microelectronic layer. The method is particularly useful for forming gate electrodes for use within field effect transistors for use within semiconductor integrated circuit microelectronic fabrications.

摘要翻译： 用于等离子体蚀刻处理在衬底上形成的微电子层的等离子体蚀刻方法包括两步等离子体蚀刻方法。 在第一步骤中，使用采用优化以测量微电子层的厚度的第一检测装置的第一等离子体蚀刻方法来蚀刻微电子层。 第一检测装置控制第一等离子体蚀刻方法在到达衬底之前停止，从而从微电子层形成部分蚀刻的微电子层。 在第二步骤中，蚀刻部分蚀刻的微电子层，同时采用采用优化以检测衬底的第二检测装置的第二等离子体蚀刻方法。 当蚀刻部分蚀刻的微电子层以形成完全蚀刻的微电子层时，第二检测装置控制第二蚀刻方法停止在基板上。 该方法特别适用于形成在半导体集成电路微电子制造中使用的场效应晶体管内使用的栅电极。

公开(公告)号：US06503848B1

公开(公告)日：2003-01-07

申请号：US09989804

申请日：2001-11-20

申请人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Huan-Just Lin ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Huan-Just Lin ,  Hun-Jan Tao

IPC分类号： H01L21469

CPC分类号： H01L21/32115 ,  H01L21/31055 ,  H01L21/3127 ,  H01L21/32137

摘要： A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.

摘要翻译： 公开了一种用于平滑多晶硅层的顶表面的方法，由于多晶硅颗粒的形成，沉积的多晶硅层具有粗糙的顶表面。 使用化学气相沉积法沉积聚合物，如CxFyBrz。 聚合物层的厚度足够大，使得聚合物的顶表面至少在多晶硅层顶表面上的晶粒峰值之上的临界距离。 然后使用以相同蚀刻速率蚀刻聚合物和多晶硅的回蚀法蚀刻掉聚合物层和多晶硅层的一部分。 这导致一层多晶硅在整个多晶硅层上具有平滑的顶表面和相同的厚度。

公开(公告)号：US07390753B2

公开(公告)日：2008-06-24

申请号：US11274109

申请日：2005-11-14

申请人： Li-Te Lin ,  Yui Wang ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Li-Te Lin ,  Yui Wang ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/302

CPC分类号： G03F7/40 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.

摘要翻译： 公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。 该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层， 在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。 优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

公开(公告)号：US20070111110A1

公开(公告)日：2007-05-17

申请号：US11274109

申请日：2005-11-14

申请人： Li-Te Lin ,  Yui Wang ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Li-Te Lin ,  Yui Wang ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： G03F1/00 ,  C03C15/00 ,  G03C5/00

CPC分类号： G03F7/40 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.

摘要翻译： 公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。 该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层， 在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。 优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

公开(公告)号：US20050092348A1

公开(公告)日：2005-05-05

申请号：US10701708

申请日：2003-11-05

申请人： Ju-Chien Chiang ,  Ming-Huan Tsai ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Ju-Chien Chiang ,  Ming-Huan Tsai ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： B08B3/08 ,  B08B3/12 ,  C11D3/39 ,  C11D7/08 ,  C11D11/00 ,  H01L21/306 ,  H01L21/311

CPC分类号： H01L21/02052 ,  B08B3/08 ,  B08B3/12 ,  C11D3/3947 ,  C11D7/08 ,  C11D11/0047 ,  H01L21/31122

摘要： The present invention provides aqueous compositions for cleaning integrated circuit substrates. Specifically, in the cleaning of an integrated circuit substrate, disclosed is a method for removing the by-products of the high-k dielectric dry etch process from the integrated circuit substrate, the method including: contacting the integrated circuit substrate with an aqueous composition including an amount, effective for the purpose of a (a) hydrogen fluoride, followed by (b) a mixture of hydrogen peroxide with a compound selected from the group consisting of ammonium hydroxide, hydrochloric acid and sulfuric acid.

摘要翻译： 本发明提供用于清洁集成电路基板的水性组合物。 具体地，在集成电路基板的清洗中，公开了从集成电路基板除去高介电常数干蚀刻工艺的副产物的方法，该方法包括：使集成电路基板与水性组合物接触，所述水性组合物包括 （a）氟化氢，其次是（b）过氧化氢与选自氢氧化铵，盐酸和硫酸的化合物的混合物的量。

公开(公告)号：US20060205224A1

公开(公告)日：2006-09-14

申请号：US11318934

申请日：2005-12-27

申请人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

公开(公告)号：US20050133827A1

公开(公告)日：2005-06-23

申请号：US10738239

申请日：2003-12-17

申请人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L29/745

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

摘要翻译： 公开了用于形成用于半导体器件的超窄栅极的大规模修整。 蚀刻在半导体晶片上的图案化软掩模层下方的半导体晶片上的硬掩模层，以使硬掩模层的宽度变窄。 修剪硬掩模层以进一步缩小已经去除软掩模层的硬掩模层的宽度。 蚀刻半导体晶片上的硬掩模层下方的至少栅极电极层，导致栅极电极层的宽度与被修整的硬掩模层的宽度基本相同。 蚀刻的栅极电极层形成半导体晶片上的超窄栅电极，其中硬掩模层被去除。

公开(公告)号：US07378713B2

公开(公告)日：2008-05-27

申请号：US11552704

申请日：2006-10-25

申请人： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

发明人： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

IPC分类号： H01L27/092 ,  H01L29/423

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

摘要： Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.

摘要翻译： 具有双金属栅极结构的半导体器件及其制造方法。 提供了具有由绝缘层分隔开的第一掺杂区域和第二掺杂区域的半导体衬底。 在第一掺杂区上形成第一金属栅叠层，在第二掺杂区上形成第二金属栅叠层。 密封层设置在第一栅极堆叠和第二栅极叠层的侧壁上。 第一金属栅叠层包括界面层，界面层上的高k电介质层，高k电介质层上的第一金属层，第一金属层上的金属插入层，金属上的第二金属层 插入层和第二金属层上的多晶硅层。 第二金属栅堆叠包括界面层，界面层上的高k电介质层，高k电介质层上的第二金属层和第二金属层上的多晶硅层。

公开(公告)号：US20080093675A1

公开(公告)日：2008-04-24

申请号：US11583634

申请日：2006-10-18

申请人： Liang-Gi Yao ,  Shiang-Bau Wang ,  Huan-Just Lin ,  Peng-Fu Hsu ,  Jin Ying ,  Hun-Jan Tao

发明人： Liang-Gi Yao ,  Shiang-Bau Wang ,  Huan-Just Lin ,  Peng-Fu Hsu ,  Jin Ying ,  Hun-Jan Tao

IPC分类号： H01L29/76

CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.

摘要翻译： 半导体结构包括衬底，衬底上的栅极堆叠，与栅极堆叠相邻的源极/漏极区域，源极/漏极区域上的源极/漏极硅化物区域，源极/漏极硅化物区域上的保护层，其中 栅极叠层上的区域基本上没有保护层，以及在保护层上方并且在栅极堆叠上延伸的接触蚀刻停止层（CESL）。

公开(公告)号：USRE39913E1

公开(公告)日：2007-11-06

申请号：US10443924

申请日：2003-05-22

申请人： Hun-Jan Tao ,  Huan-Just Lin ,  Fang-Cheng Chen

发明人： Hun-Jan Tao ,  Huan-Just Lin ,  Fang-Cheng Chen

IPC分类号： G03F9/00

CPC分类号： G03F7/70625 ,  G03F7/40 ,  H01L22/20 ,  Y10S438/949

摘要： The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle generated from this modified data file, the pattern is formed in photoresist and the resulting CD value is determined. If this turns out be outside (above) the acceptable CD range, the amount of deviation from the ideal CD value is determined and fed into suitable software that calculates the control parameters (usually time) for an ashing routine. After ashing, the lines will have been reduced in width by the amount necessary to obtain the correct CD. A fringe benefit of this trimming process is that edge roughness of the photoresist lines is reduced and line feet are removed.

摘要翻译： 本发明是减少CD从晶片到晶片的变化的方法。 它首先将原始图案数据文件中的所有行宽增加一个固定的量，这足以确保所有行都比最低可接受的CD值宽。 使用由该修改的数据文件生成的掩模版，在光致抗蚀剂中形成图案，并确定所得到的CD值。 如果事实证明在可接受的CD范围之外（以上），则确定与理想CD值的偏差量，并将其馈送到计算灰化程序的控制参数（通常为时间）的合适软件中。 灰化后，线条的宽度减小了获得正确CD所需的量。 这种修整过程的附带优点是减少了光致抗蚀剂线的边缘粗糙度并且去除了线脚。