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11 条记录 (耗时 0.025 秒)

    METHOD OF FORMING AN INTERCONNECT STRUCTURE
    1.
    发明申请
    METHOD OF FORMING AN INTERCONNECT STRUCTURE 失效
    形成互连结构的方法

    公开(公告)号：US20060223323A1

    公开(公告)日：2006-10-05

    申请号：US11424359

    申请日：2006-06-15

    申请人： Liang-Yuh Chen ,  Daniel Carl ,  Israel Beinglass

    发明人： Liang-Yuh Chen ,  Daniel Carl ,  Israel Beinglass

    IPC分类号： H01L21/311

    CPC分类号： C23C16/45589 ,  C23C14/046 ,  C23C16/045 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76865

    摘要： A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.

    摘要翻译： 公开了一种在具有高纵横比特征的基底上形成层的方法。 该层由包含一种或多种工艺气体和一种或多种蚀刻物质的气体混合物形成。 一种或多种工艺气体反应以在衬底上沉积材料层。 结合材料层沉积，蚀刻物质选择性地去除与高纵横比特征开口相邻的沉积材料层的部分，以无空隙和/或无缝隙的方式填充这些特征。 材料层可以使用物理气相沉积（PVD）和/或化学气相沉积（CVD）技术沉积在衬底上。

    METHOD OF FORMING A TRENCH STRUCTURE
    2.
    发明申请
    METHOD OF FORMING A TRENCH STRUCTURE 失效
    形成TRENCH结构的方法

    公开(公告)号：US20060223322A1

    公开(公告)日：2006-10-05

    申请号：US11424351

    申请日：2006-06-15

    申请人： Liang-Yuh Chen ,  Daniel Carl ,  Israel Beinglass

    发明人： Liang-Yuh Chen ,  Daniel Carl ,  Israel Beinglass

    IPC分类号： H01L21/311

    CPC分类号： C23C16/45589 ,  C23C14/046 ,  C23C16/045 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76865

    摘要： A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.

    摘要翻译： 公开了一种在具有高纵横比特征的基底上形成层的方法。 该层由包含一种或多种工艺气体和一种或多种蚀刻物质的气体混合物形成。 一种或多种工艺气体反应以在衬底上沉积材料层。 结合材料层沉积，蚀刻物质选择性地去除与高纵横比特征开口相邻的沉积材料层的部分，以无空隙和/或无缝隙的方式填充这些特征。 材料层可以使用物理气相沉积（PVD）和/或化学气相沉积（CVD）技术沉积在衬底上。

    Method for dishing reduction and feature passivation in polishing processes
    4.
    发明申请
    Method for dishing reduction and feature passivation in polishing processes 审中-公开
    抛光过程中凹陷减少和特征钝化的方法

    公开(公告)号：US20050202677A1

    公开(公告)日：2005-09-15

    申请号：US11114936

    申请日：2005-04-25

    申请人： Wei-Yung Hsu ,  Liang-Yuh Chen ,  Ratson Morad ,  Daniel Carl

    发明人： Wei-Yung Hsu ,  Liang-Yuh Chen ,  Ratson Morad ,  Daniel Carl

    IPC分类号： H01L21/288 ,  H01L21/321 ,  C25C3/00

    CPC分类号： H01L21/7684 ,  H01L21/3212

    摘要： Methods and apparatus for planarizing a substrate surface are provided. In one aspect, a method is provided for planarizing a substrate surface including polishing a first conductive material to a barrier layer material, depositing a second conductive material on the first conductive material by an electrochemical deposition technique, and polishing the second conductive material and the barrier layer material to a dielectric layer. In another aspect, a processing system is provided for forming a planarized layer on a substrate, the processing system including a computer based controller configured to cause the system to polish a first conductive material to a barrier layer material, deposit a second conductive material on the first conductive material by an electrochemical deposition technique, and polish the second conductive material and the barrier layer material to a dielectric layer.

    摘要翻译： 提供了用于平坦化基板表面的方法和装置。 在一个方面，提供了一种用于平坦化衬底表面的方法，包括将第一导电材料抛光到阻挡层材料，通过电化学沉积技术在第一导电材料上沉积第二导电材料，以及抛光第二导电材料和屏障 层材料到介电层。 在另一方面，提供一种用于在衬底上形成平坦化层的处理系统，所述处理系统包括基于计算机的控制器，所述计算机控制器被配置为使所述系统将第一导电材料抛光至阻挡层材料，将第二导电材料沉积在所述第二导电材料上 通过电化学沉积技术的第一导电材料，并将第二导电材料和阻挡层材料抛光到介电层。

    Planarization of substrates using electrochemical mechanical polishing
    5.
    发明申请
    Planarization of substrates using electrochemical mechanical polishing 审中-公开
    使用电化学机械抛光对基板进行平面化

    公开(公告)号：US20050056537A1

    公开(公告)日：2005-03-17

    申请号：US10972884

    申请日：2004-10-25

    申请人： Liang-Yuh Chen ,  Wei-Yung Hsu ,  Alain Duboust ,  Ratson Morad ,  Daniel Carl

    发明人： Liang-Yuh Chen ,  Wei-Yung Hsu ,  Alain Duboust ,  Ratson Morad ,  Daniel Carl

    IPC分类号： B24B37/00 ,  B23H5/08 ,  B24B37/04 ,  H01L21/304 ,  H01L21/316 ,  B23H5/00

    CPC分类号： B23H5/08

    摘要： A method and apparatus are provided for planarizing a material layer on a substrate. In one aspect, a method is provided for processing a substrate including forming a passivation layer on a substrate surface, polishing the substrate in an electrolyte solution, applying an anodic bias to the substrate surface, and removing material from at least a portion of the substrate surface. In another aspect, an apparatus is provided which includes a partial enclosure, polishing article, a cathode, a power source, a substrate carrier movably disposed above the polishing article, and a computer based controller to position a substrate in an electrolyte solution to form a passivation layer on a substrate surface, to polish the substrate in the electrolyte solution with the polishing article, and to apply an anodic bias to the substrate surface or polishing article to remove material from at least a portion of the substrate surface.

    摘要翻译： 提供了一种用于平坦化衬底上的材料层的方法和装置。 在一个方面，提供一种用于处理衬底的方法，包括在衬底表面上形成钝化层，在电解质溶液中抛光衬底，向衬底表面施加阳极偏压，以及从衬底的至少一部分去除材料 表面。 在另一方面，提供了一种装置，其包括部分外壳，抛光制品，阴极，电源，可移动地设置在抛光制品上方的基板载体，以及基于计算机的控制器，以将基板定位在电解质溶液中以形成 在衬底表面上的钝化层，用抛光制品抛光电解质溶液中的衬底，并将阳极偏压施加到衬底表面或抛光制品上以从衬底表面的至少一部分去除材料。

    Method and apparatus for forming metal interconnects
    10.
    发明授权
    Method and apparatus for forming metal interconnects 失效
    用于形成金属互连的方法和装置

    公开(公告)号：US06372633B1

    公开(公告)日：2002-04-16

    申请号：US09111657

    申请日：1998-07-08

    申请人： Dan Maydan ,  Ashok K. Sinha ,  Zheng Xu ,  Liang-Yu Chen ,  Roderick Craig Mosely ,  Daniel Carl ,  Diana Xiaobing Ma ,  Yan Ye ,  Wen Chiang Tu

    发明人： Dan Maydan ,  Ashok K. Sinha ,  Zheng Xu ,  Liang-Yu Chen ,  Roderick Craig Mosely ,  Daniel Carl ,  Diana Xiaobing Ma ,  Yan Ye ,  Wen Chiang Tu

    IPC分类号： H01L214763

    CPC分类号： H01L21/76838 ,  H01L21/32136 ,  H01L21/76885

    摘要： The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.

    摘要翻译： 本发明提供了一种用于形成可靠互连的方法和装置，其中使插塞或通孔上的线重叠最小化或消除。 在一个方面，由诸如钨的导电材料构成的阻挡塞沉积在通孔上，以在线蚀刻期间提供蚀刻停止并且防止金属（例如铜）扩散到周围的介电材料中，如果线 在通道上不对齐。 此外，阻挡塞防止互连的电阻的总体降低，并且能够使用反应离子蚀刻来形成金属线。 在另一方面，使用反应离子蚀刻技术来选择性地蚀刻金属线和阻挡层，以提供对金属线，然后是屏障，然后是通孔或插塞的选择性的受控蚀刻工艺。