Multi-device memory serial architecture
    8.
    发明授权
    Multi-device memory serial architecture 有权
    多设备内存串行架构

    公开(公告)号:US09575662B2

    公开(公告)日:2017-02-21

    申请号:US14670978

    申请日:2015-03-27

    Abstract: Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller.

    Abstract translation: 本文公开的主题涉及包括存储器阵列,通过另一存储器件直接或间接地与存储器控制器接口的第一端口,与另一个存储器件接口的第二端口以及用于选择性地电连接存储器 控制器连接到通向第二端口或存储器阵列的电路路径,其中开关可以响应于存储器控制器产生的信号。

    MULTI-DEVICE MEMORY SERIAL ARCHITECTURE
    9.
    发明申请
    MULTI-DEVICE MEMORY SERIAL ARCHITECTURE 有权
    多设备存储器串行架构

    公开(公告)号:US20150199133A1

    公开(公告)日:2015-07-16

    申请号:US14670978

    申请日:2015-03-27

    Abstract: Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller.

    Abstract translation: 本文公开的主题涉及包括存储器阵列,通过另一存储器件直接或间接地与存储器控制器接口的第一端口,与另一存储器件接口的第二端口以及用于选择性地电连接存储器 控制器连接到通向第二端口或存储器阵列的电路路径,其中开关可以响应于存储器控制器产生的信号。

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