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    High-density nonvolatile memory and methods of making the same
    3.
    发明授权
    High-density nonvolatile memory and methods of making the same 有权
    高密度非易失性存储器及其制作方法

    公开(公告)号：US08383478B2

    公开(公告)日：2013-02-26

    申请号：US13195518

    申请日：2011-08-01

    申请人： Scott Brad Herner ,  Maitreyee Mahajani

    发明人： Scott Brad Herner ,  Maitreyee Mahajani

    IPC分类号： H01L21/336

    CPC分类号： G11C5/02 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/1021 ,  H01L27/148 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.

    摘要翻译： 提供了非易失存储器单元及其形成方法，所述方法包括在衬底上方的第一高度处形成第一导体; 在所述第一导体上形成第一柱状半导体元件，其中所述第一柱状半导体元件包括第一导电类型的第一重掺杂层，在所述第一重掺杂层上方并与其接触的第二轻掺杂层，以及 第二导电类型的第三重掺杂层在第二轻掺杂层上方并与第二轻掺杂层接触，第二导电类型与第一导电类型相反; 在所述第一柱状半导体元件的所述第三重掺杂层的上方形成第一介电反熔丝; 以及在所述第一介电反熔丝之上形成第二导体。

    LOW TEMPERATURE ALD Si02
    6.
    发明申请
    LOW TEMPERATURE ALD Si02 有权
    低温ALD Si02

    公开(公告)号：US20100227061A1

    公开(公告)日：2010-09-09

    申请号：US12788131

    申请日：2010-05-26

    申请人： Maitreyee Mahajani ,  Yi-Chiau Huang ,  Brendan McDougall

    发明人： Maitreyee Mahajani ,  Yi-Chiau Huang ,  Brendan McDougall

    IPC分类号： C23C16/40

    CPC分类号： C23C16/402 ,  C23C16/45534

    摘要： The present invention generally comprises a silicon dioxide atomic layer deposition method. By providing pyridine as a catalyst, water may be utilized as the oxidization source while depositing at a low temperature. Prior to exposing the substrate to the water, the substrate may be exposed to a pyridine soak process. Additionally, the water may be co-flowed to the chamber with the pyridine through separate conduits to reduce interaction prior to entering the chamber. Alternatively, the pyridine may be co-flowed with a silicon precursor that does not react with pyridine.

    摘要翻译： 本发明通常包括二氧化硅原子层沉积方法。 通过提供吡啶作为催化剂，可以在低温下沉积时使用水作为氧化源。 在将基底暴露于水之前，可以将底物暴露于吡啶浸泡过程。 此外，水可以通过单独的导管与吡啶共同流到室中，以减少进入室之前的相互作用。 或者，吡啶可以与不与吡啶反应的硅前体共流。

    HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME
    7.
    发明申请
    HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME 有权
    高密度非易失性存储器及其制造方法

    公开(公告)号：US20090261343A1

    公开(公告)日：2009-10-22

    申请号：US12477216

    申请日：2009-06-03

    申请人： S. Brad Herner ,  Maitreyee Mahajani

    发明人： S. Brad Herner ,  Maitreyee Mahajani

    IPC分类号： H01L29/04 ,  H01L21/20

    CPC分类号： G11C5/02 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/1021 ,  H01L27/148 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.

    摘要翻译： 提供了非易失存储器单元及其形成方法，所述方法包括在衬底上方的第一高度处形成第一导体; 在所述第一导体上形成第一柱状半导体元件，其中所述第一柱状半导体元件包括第一导电类型的第一重掺杂层，在所述第一重掺杂层上方并与其接触的第二轻掺杂层，以及 第二导电类型的第三重掺杂层在第二轻掺杂层上方并与第二轻掺杂层接触，第二导电类型与第一导电类型相反; 在所述第一柱状半导体元件的所述第三重掺杂层的上方形成第一介电反熔丝; 以及在所述第一介电反熔丝之上形成第二导体。

    Dual-gate device and method
    8.
    发明授权
    Dual-gate device and method 有权
    双栅极器件及方法

    公开(公告)号：US07495337B2

    公开(公告)日：2009-02-24

    申请号：US11671859

    申请日：2007-02-06

    申请人： Andrew J. Walker ,  Maitreyee Mahajani

    发明人： Andrew J. Walker ,  Maitreyee Mahajani

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L27/1203 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11568 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  Y10S438/951

    摘要： A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material sufficient to isolate the semiconductor devices from electrostatically interacting. In one embodiment, one of the semiconductor devices includes a charge storing layer, such as an ONO layer. Such a dual-gate device is suitable for use in a non-volatile memory array.

    摘要翻译： 双栅极器件形成在半导体衬底上并与半导体衬底绝缘，半导体衬底可以包括可以互连到双栅极器件的附加功能电路。 双栅极器件包括形成在公共有源半导体区域的相对表面上的两个半导体器件，其提供足以将半导体器件与静电相互作用隔离的厚度和材料。 在一个实施例中，半导体器件之一包括诸如ONO层的电荷存储层。 这种双栅极器件适用于非易失性存储器阵列。

    DUAL-GATE DEVICE AND METHOD
    9.
    发明申请
    DUAL-GATE DEVICE AND METHOD 有权
    双门装置和方法

    公开(公告)号：US20070126033A1

    公开(公告)日：2007-06-07

    申请号：US11671859

    申请日：2007-02-06

    申请人： Andrew Walker ,  Maitreyee Mahajani

    发明人： Andrew Walker ,  Maitreyee Mahajani

    IPC分类号： H01L29/768

    CPC分类号： H01L27/1203 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11568 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  Y10S438/951

    摘要： A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material sufficient to isolate the semiconductor devices from electrostatically interacting. In one embodiment, one of the semiconductor devices includes a charge storing layer, such as an ONO layer. Such a dual-gate device is suitable for use in a non-volatile memory array.

    摘要翻译： 双栅极器件形成在半导体衬底上并与半导体衬底绝缘，半导体衬底可以包括可以互连到双栅极器件的附加功能电路。 双栅极器件包括形成在公共有源半导体区域的相对表面上的两个半导体器件，其提供足以将半导体器件与静电相互作用隔离的厚度和材料。 在一个实施例中，半导体器件之一包括诸如ONO层的电荷存储层。 这种双栅极器件适用于非易失性存储器阵列。

    High-density three-dimensional memory
    10.
    发明授权
    High-density three-dimensional memory 有权
    高密度三维记忆

    公开(公告)号：US06995422B2

    公开(公告)日：2006-02-07

    申请号：US10855778

    申请日：2004-05-26

    申请人： S. Brad Herner ,  Maitreyee Mahajani

    发明人： S. Brad Herner ,  Maitreyee Mahajani

    IPC分类号： H01L29/788

    CPC分类号： G11C5/02 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/1021 ,  H01L27/148 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

    摘要翻译： 一种用于制造密度增加的三维单片存储器的改进方法。 该方法包括形成优选包含钨的导体，然后填充和平坦化; 在形成半导体元件的导体之上，优选地包括两个二极管部分和反熔丝，然后填充和平坦化; 并在多层故事中继续形成导体和半导体元件。 处理步骤的布置和材料的选择降低了每个存储单元的纵横比，提高了间隙填充的可靠性并防止蚀刻底切。