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公开(公告)号：US06933235B2
公开(公告)日：2005-08-23
申请号：US10302714
申请日：2002-11-21
IPC分类号： H01L21/268 , H01L21/28 , H01L21/306 , H01L21/311 , H01L21/316 , H01L21/32 , H01L29/51 , H01L21/302
CPC分类号： H01L21/02238 , H01L21/02052 , H01L21/2686 , H01L21/28185 , H01L21/28194 , H01L21/31116 , H01L21/31604 , H01L21/31645 , H01L21/31662 , H01L21/32 , H01L29/517 , H01L29/518
摘要： A method of processing a substrate is disclosed. The method includes depositing a dielectric layer having a metal oxide on a substrate. A portion of the dielectric layer is removed to form a dielectric structure, thereby exposing a surface of the substrate. For example, the dielectric layer may be patterned using standard photolithographic techniques and etching. An oxide layer is then formed on the exposed surface of the substrate. The oxide layer may be formed using ozone that is generated using ultraviolet radiation. After the oxide layer is formed, it is removed using an etching process.
摘要翻译： 公开了一种处理衬底的方法。 该方法包括在衬底上沉积具有金属氧化物的电介质层。 去除介电层的一部分以形成电介质结构，从而暴露衬底的表面。 例如，可以使用标准光刻技术和蚀刻对电介质层进行图案化。 然后在基板的暴露表面上形成氧化物层。 可以使用使用紫外线辐射产生的臭氧形成氧化物层。 在形成氧化物层之后，使用蚀刻工艺除去氧化物层。
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2.发明授权Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow 有权将高k金属栅极堆叠集成到直接硅键（DSB）混合取向技术（HOT）pMOS工艺流程中公开(公告)号：US07943479B2
公开(公告)日：2011-05-17
申请号：US12193956
申请日：2008-08-19
IPC分类号： H01L21/76
CPC分类号： H01L29/045 , H01L21/26506 , H01L21/28088 , H01L21/28202 , H01L21/823807 , H01L21/823828 , H01L29/4966 , H01L29/517
摘要： A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is deposited over the first crystal orientation layer that comprises an insulation layer, a high-k dielectric layer, a first metal layer, and a second metal layer thereon.
摘要翻译： 一种用于半导体处理的方法提供了具有第一晶体取向层和第二晶体取向层的DSB半导体本体，以及设置在第一和第二晶体取向之间的边界区域。 在第一晶体取向层上沉积高k金属栅极堆叠，其上包括绝缘层，高k电介质层，第一金属层和第二金属层。
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3.发明授权Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication 有权用于减轻浅沟槽隔离制造的蚀刻停止限幅的方法和系统公开(公告)号：US07625807B2
公开(公告)日：2009-12-01
申请号：US11678107
申请日：2007-02-23
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/823807 , H01L21/823878
摘要： The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.
摘要翻译： 本发明通过在沟槽填充操作期间保持蚀刻停止层（206）的形状和密度来促进半导体制造。 通过在沟槽填充操作之前在蚀刻停止层（206）上形成保护合金衬垫层（310）来保持蚀刻停止层（206）的形状和密度。 保护合金衬套（310）由对沟槽填充操作中使用的材料具有耐受性的合金构成。 结果，减轻了对蚀刻停止层（206）的削波和/或损伤，从而有利于采用蚀刻停止层（206）的随后的平坦化工艺。 此外，形成的保护合金（310）的厚度和组成（1706）的选择产生施加到未成形晶体管器件的沟道区域的应力量和类型（1704），最终提供了沟道迁移率的改善。
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4.发明申请INTEGRATION OF HIGH-K METAL-GATE STACK INTO DIRECT SILICON BONDING (DSB) HYBRID ORIENTATION TECHNOLOGY (HOT) PMOS PROCESS FLOW 有权将高K金属叠层叠加到直接硅粘结（DSB）混合方向技术（热）PMOS工艺流程公开(公告)号：US20100047993A1
公开(公告)日：2010-02-25
申请号：US12193956
申请日：2008-08-19
IPC分类号： H01L21/77
CPC分类号： H01L29/045 , H01L21/26506 , H01L21/28088 , H01L21/28202 , H01L21/823807 , H01L21/823828 , H01L29/4966 , H01L29/517
摘要： A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is deposited over the first crystal orientation layer that comprises an insulation layer, a high-k dielectric layer, a first metal layer, and a second metal layer thereon.
摘要翻译： 一种用于半导体处理的方法提供了具有第一晶体取向层和第二晶体取向层的DSB半导体本体，以及设置在第一和第二晶体取向之间的边界区域。 在第一晶体取向层上沉积高k金属栅极堆叠，其上包括绝缘层，高k电介质层，第一金属层和第二金属层。
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5.发明授权Top surface roughness reduction of high-k dielectric materials using plasma based processes 有权使用基于等离子体工艺的高k介电材料的顶表面粗糙度降低公开(公告)号：US07115530B2
公开(公告)日：2006-10-03
申请号：US10726987
申请日：2003-12-03
IPC分类号： H01L21/31
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
摘要翻译： 具有介电常数大于二氧化硅的电介质层的半导体器件的系统和方法包括在基片上沉积电介质层并对介电层进行等离子体以减小电介质层中的顶表面粗糙度。
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