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    Method of making trench DRAM
    1.
    发明授权
    Method of making trench DRAM 失效
    制造沟槽DRAM的方法

    公开(公告)号：US6066526A

    公开(公告)日：2000-05-23

    申请号：US12070

    申请日：1998-01-22

    申请人： Mark Charles Hakey ,  William Hsioh-Lien Ma

    发明人： Mark Charles Hakey ,  William Hsioh-Lien Ma

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/10873

    摘要： A process sequence for an eight square folded bit line dynamic random access memory (DRAM) cell allows a transfer device channel length of two lithographic features. The method uses conventional processing techniques with no spacer defined features and uses conventional structures. The process sequence starts with deep trench (DT) processing, followed by deposition of insulator such as SiO2, planarization and pad strip. Then gate insulator and gate conductor are deposited. Also a pad or thin insulator can be deposited at this stage. The structure is etched using a shallow trench isolation mask and filled with SiO.sub.2. The gate conductor such as polysilicon is etched with a contact mask and reactive ion etching. If not previously deposited, a thin insulator is deposited. The structure is etched again with a gate poly contact mask. A gate conductor is then deposited. After a final etch, wiring is added.

    摘要翻译： 用于八平方折叠位线动态随机存取存储器（DRAM）单元的处理顺序允许两个光刻特征的传输设备通道长度。 该方法使用没有间隔物限定特征的常规加工技术，并且使用常规结构。 工艺顺序从深沟（DT）处理开始，然后沉积诸如SiO 2，平坦化和焊盘条之类的绝缘体。 然后沉积栅极绝缘体和栅极导体。 在此阶段也可以沉积垫或薄绝缘体。 使用浅沟槽隔离掩模蚀刻该结构并填充SiO 2。 用接触掩膜和反应离子蚀刻蚀刻诸如多晶硅的栅极导体。 如果先前未沉积，则沉积薄的绝缘体。 用栅极聚接触掩模再次蚀刻该结构。 然后沉积栅极导体。 最终蚀刻后，加入接线。

    Method of fabricating trench for SOI merged logic DRAM
    3.
    发明授权
    Method of fabricating trench for SOI merged logic DRAM 失效
    SOI合并逻辑DRAM制造沟槽的方法

    公开(公告)号：US06548345B2

    公开(公告)日：2003-04-15

    申请号：US09765560

    申请日：2001-01-19

    申请人： Mark Charles Hakey ,  William Hsioh-Lien Ma

    发明人： Mark Charles Hakey ,  William Hsioh-Lien Ma

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/10894

    摘要： Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

    摘要翻译： 提供了在具有相对较厚的掩埋氧化物区域的绝缘体上硅（SOI）晶片上形成合并的逻辑DRAM器件的方法，其中将深沟槽蚀刻到SOI衬底中而不通过掩埋氧化物层进行蚀刻。 本发明的方法提供了高性能的SOI合并逻辑DRAM器件。

    Method of fabricating trench for SOI merged logic DRAM
    4.
    发明授权
    Method of fabricating trench for SOI merged logic DRAM 失效
    SOI合并逻辑DRAM制造沟槽的方法

    公开(公告)号：US06232170B1

    公开(公告)日：2001-05-15

    申请号：US09334094

    申请日：1999-06-16

    申请人： Mark Charles Hakey ,  William Hsioh-Lien Ma

    发明人： Mark Charles Hakey ,  William Hsioh-Lien Ma

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/10894

    摘要： Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

    摘要翻译： 提供了在具有相对较厚的掩埋氧化物区域的绝缘体上硅（SOI）晶片上形成合并的逻辑DRAM器件的方法，其中将深沟槽蚀刻到SOI衬底中而不通过掩埋氧化物层进行蚀刻。 本发明的方法提供了高性能的SOI合并逻辑DRAM器件。

    Alignment methodology for lithography
    6.
    发明授权
    Alignment methodology for lithography 失效
    光刻对准方法

    公开(公告)号：US06342323B1

    公开(公告)日：2002-01-29

    申请号：US09523796

    申请日：2000-03-13

    申请人： William Hsioh-Lien Ma ,  David Vaclay Horak ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Mark Charles Hakey

    发明人： William Hsioh-Lien Ma ,  David Vaclay Horak ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Mark Charles Hakey

    IPC分类号： G03F900

    CPC分类号： G03F9/7084 ,  G03F9/7046

    摘要： An improved alignment methodology for lithography. In the method, a third level is aligned to two previous levels, where the alignment mark location for the third level is calculated based upon the two previous levels in both the x- and y-directions. A preferred embodiment of the invention relates to a lithography alignment method for aligning a third level of a semiconductor device relative to first and second previous levels of the device. The method comprises the steps of forming first and second patterns at the first and second levels respectively, and determining offsets of the first and second patterns in two orthoginal directions. An optimum location for a third pattern in the third level is then determined based on an average of the offsets of the first and second patterns.

    摘要翻译： 改进光刻对准方法。 在该方法中，第三级与两个先前级别对准，其中基于x和y方向上的两个先前级别来计算第三级的对准标记位置。 本发明的优选实施例涉及一种用于使半导体器件的第三级相对于器件的第一和第二级别对准的光刻对准方法。 该方法包括以下步骤：分别在第一和第二电平处形成第一和第二图案，以及确定两个原始方向上的第一和第二图案的偏移。 然后基于第一和第二图案的偏移的平均值来确定第三级中的第三图案的最佳位置。

    Phase change memory cell with vertical transistor
    7.
    发明授权
    Phase change memory cell with vertical transistor 有权
    具有垂直晶体管的相变存储单元

    公开(公告)号：US07932167B2

    公开(公告)日：2011-04-26

    申请号：US11771457

    申请日：2007-06-29

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    IPC分类号： H01L21/44

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

    摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

    摘要翻译： 部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。 岛形成在下电极特征上并具有一个或多个侧壁。 它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。 牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。 栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。 最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。 响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

    Well isolation trenches (WIT) for CMOS devices
    8.
    发明授权
    Well isolation trenches (WIT) for CMOS devices 失效
    用于CMOS器件的隔离沟槽（WIT）

    公开(公告)号：US07737504B2

    公开(公告)日：2010-06-15

    申请号：US11759981

    申请日：2007-06-08

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L29/772

    CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

    摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

    摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。