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公开(公告)号：US06548345B2
公开(公告)日：2003-04-15
申请号：US09765560
申请日：2001-01-19
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/76264 , H01L21/76283 , H01L27/10894
摘要： Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.
摘要翻译： 提供了在具有相对较厚的掩埋氧化物区域的绝缘体上硅（SOI）晶片上形成合并的逻辑DRAM器件的方法，其中将深沟槽蚀刻到SOI衬底中而不通过掩埋氧化物层进行蚀刻。 本发明的方法提供了高性能的SOI合并逻辑DRAM器件。
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公开(公告)号：US06232170B1
公开(公告)日：2001-05-15
申请号：US09334094
申请日：1999-06-16
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/76264 , H01L21/76283 , H01L27/10894
摘要： Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.
摘要翻译： 提供了在具有相对较厚的掩埋氧化物区域的绝缘体上硅（SOI）晶片上形成合并的逻辑DRAM器件的方法，其中将深沟槽蚀刻到SOI衬底中而不通过掩埋氧化物层进行蚀刻。 本发明的方法提供了高性能的SOI合并逻辑DRAM器件。
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3.发明授权Methods of making a trench storage DRAM cell including a step transfer device 失效制造包括步进转移装置的沟槽存储DRAM单元的方法
公开(公告)号：US6063658A
公开(公告)日：2000-05-16
申请号：US172865
申请日：1998-10-15
申请人： David Vaclav Horak , Toshiharu Furukawa , Steven John Holmes , Mark Charles Hakey , William Hsioh-Lien Ma , Jack Allan Mandelman
发明人： David Vaclav Horak , Toshiharu Furukawa , Steven John Holmes , Mark Charles Hakey , William Hsioh-Lien Ma , Jack Allan Mandelman
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.
摘要翻译： 存储单元，包括衬底，衬底中的至少一个深沟槽电容器，设置在所述至少一个深沟槽电容器的至少一部分上的所述衬底中的至少一个FET以及所述衬底中的至少一个隔离区域， 至少一个FET并且具有比所述至少一个FET更大的深度。 所述至少一个FET包括设置在所述至少一个深沟槽电容器的至少一部分上的栅极和布置在栅极的相邻侧上的掺杂区域，并且通过绝缘层与栅极分离。
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公开(公告)号：US6066526A
公开(公告)日：2000-05-23
申请号：US12070
申请日：1998-01-22
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10873
摘要： A process sequence for an eight square folded bit line dynamic random access memory (DRAM) cell allows a transfer device channel length of two lithographic features. The method uses conventional processing techniques with no spacer defined features and uses conventional structures. The process sequence starts with deep trench (DT) processing, followed by deposition of insulator such as SiO2, planarization and pad strip. Then gate insulator and gate conductor are deposited. Also a pad or thin insulator can be deposited at this stage. The structure is etched using a shallow trench isolation mask and filled with SiO.sub.2. The gate conductor such as polysilicon is etched with a contact mask and reactive ion etching. If not previously deposited, a thin insulator is deposited. The structure is etched again with a gate poly contact mask. A gate conductor is then deposited. After a final etch, wiring is added.
摘要翻译： 用于八平方折叠位线动态随机存取存储器（DRAM）单元的处理顺序允许两个光刻特征的传输设备通道长度。 该方法使用没有间隔物限定特征的常规加工技术，并且使用常规结构。 工艺顺序从深沟（DT）处理开始，然后沉积诸如SiO 2，平坦化和焊盘条之类的绝缘体。 然后沉积栅极绝缘体和栅极导体。 在此阶段也可以沉积垫或薄绝缘体。 使用浅沟槽隔离掩模蚀刻该结构并填充SiO 2。 用接触掩膜和反应离子蚀刻蚀刻诸如多晶硅的栅极导体。 如果先前未沉积，则沉积薄的绝缘体。 用栅极聚接触掩模再次蚀刻该结构。 然后沉积栅极导体。 最终蚀刻后，加入接线。
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公开(公告)号：US5831301A
公开(公告)日：1998-11-03
申请号：US14523
申请日：1998-01-28
申请人： David Vaclav Horak , Toshiharu Furukawa , Steven John Holmes , Mark Charles Hakey , William Hsioh-Lien Ma , Jack Allan Mandelman
发明人： David Vaclav Horak , Toshiharu Furukawa , Steven John Holmes , Mark Charles Hakey , William Hsioh-Lien Ma , Jack Allan Mandelman
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.
摘要翻译： 存储单元，包括衬底，衬底中的至少一个深沟槽电容器，设置在所述至少一个深沟槽电容器的至少一部分上的所述衬底中的至少一个FET以及所述衬底中的至少一个隔离区域， 至少一个FET并且具有比所述至少一个FET更大的深度。 所述至少一个FET包括设置在所述至少一个深沟槽电容器的至少一部分上的栅极和布置在栅极的相邻侧上的掺杂区域，并且通过绝缘层与栅极分离。
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公开(公告)号：US06342323B1
公开(公告)日：2002-01-29
申请号：US09523796
申请日：2000-03-13
申请人： William Hsioh-Lien Ma , David Vaclay Horak , Toshiharu Furukawa , Steven J. Holmes , Mark Charles Hakey
发明人： William Hsioh-Lien Ma , David Vaclay Horak , Toshiharu Furukawa , Steven J. Holmes , Mark Charles Hakey
IPC分类号： G03F900
CPC分类号： G03F9/7084 , G03F9/7046
摘要： An improved alignment methodology for lithography. In the method, a third level is aligned to two previous levels, where the alignment mark location for the third level is calculated based upon the two previous levels in both the x- and y-directions. A preferred embodiment of the invention relates to a lithography alignment method for aligning a third level of a semiconductor device relative to first and second previous levels of the device. The method comprises the steps of forming first and second patterns at the first and second levels respectively, and determining offsets of the first and second patterns in two orthoginal directions. An optimum location for a third pattern in the third level is then determined based on an average of the offsets of the first and second patterns.
摘要翻译： 改进光刻对准方法。 在该方法中，第三级与两个先前级别对准，其中基于x和y方向上的两个先前级别来计算第三级的对准标记位置。 本发明的优选实施例涉及一种用于使半导体器件的第三级相对于器件的第一和第二级别对准的光刻对准方法。 该方法包括以下步骤：分别在第一和第二电平处形成第一和第二图案，以及确定两个原始方向上的第一和第二图案的偏移。 然后基于第一和第二图案的偏移的平均值来确定第三级中的第三图案的最佳位置。
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7.发明授权Method of sending an email to a plurality of recipients with selective treatment of attached files 失效通过选择性处理所附文件向多个接收者发送电子邮件的方法公开(公告)号：US07548952B2
公开(公告)日：2009-06-16
申请号：US10160522
申请日：2002-05-31
IPC分类号： G06F15/16
CPC分类号： G06Q10/107
摘要： A method of sending an email message having one or more attached files to a plurality of recipients allows customized treatment of each file as it is being sent to each recipient. Treatments may include different types of encryption, plain text transmission, security classification or user-defined treatments. The invention may be implemented in a client-server configuration with separate client and server programs or in a single integrated email program configuration for use on a single computer. The user is presented with a list of recipients, selects a recipient and then selects a treatment for each file to be used when that file is sent to the selected recipient. This process is repeated for each recipient and each file. A control file is generated by the client program, including the recipient information and the file treatment information for each recipient and each file. The client program sends a single copy of the email message, a single copy of each file and the control file to the server program. The server program reads the control file and prepares individualized emails for each recipient by applying the control file specified treatments for each attached file.
摘要翻译： 向多个接收者发送具有一个或多个附加文件的电子邮件消息的方法允许对每个文件进行定制处理，因为它被发送给每个接收者。 治疗可以包括不同类型的加密，纯文本传输，安全分类或用户定义的治疗。 本发明可以在具有单独的客户端和服务器程序的客户机 - 服务器配置中实现，或者在单个集成的电子邮件程序配置中用于单个计算机上。 向用户呈现收件人列表，选择收件人，然后为该文件发送到所选收件人时为每个要使用的文件选择一个处理。 每个收件人和每个文件重复此过程。 控制文件由客户程序生成，包括收件人信息和每个收件人和每个文件的文件处理信息。 客户端程序将电子邮件的单个副本，每个文件的单个副本和控制文件发送到服务器程序。 服务器程序读取控制文件，并通过对每个附件文件应用指定的控制文件来处理每个收件人的个性化电子邮件。
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8.发明授权Method of fabricating a multistack 3-dimensional high density semiconductor device 失效制造多层三维高密度半导体器件的方法公开(公告)号：US06451634B2
公开(公告)日：2002-09-17
申请号：US09925525
申请日：2001-08-10
IPC分类号： H01L2184
CPC分类号： H01L21/76251 , H01L21/76895 , H01L21/76898
摘要： A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and further comprising second active devices; and wherein the first active devices are more heat tolerant than the second active devices is provided along with a method for its fabrication.
摘要翻译： 一种包括第一层结构的多层3-D半导体结构，包括第一半导体衬底和第一有源器件; 以及包括结合到所述第一级结构并且还包括第二有源器件的SOI半导体结构的第二级结构; 并且其中所述第一有源器件与其制造方法一起提供比所述第二有源器件更耐热。
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9.发明授权Method for forming cornered images on a substrate and photomask formed thereby 失效在基板上形成圆角图像的方法和由此形成的光掩模公开(公告)号：US06184151B2
公开(公告)日：2001-02-06
申请号：US09275541
申请日：1999-03-24
申请人： William J. Adair , Richard A. Ferguson , Mark C. Hakey , Steven J. Holmes , David V. Horak , Robert K. Leidy , William Hsioh-Lien Ma , Ronald M. Martino , Song Peng
发明人： William J. Adair , Richard A. Ferguson , Mark C. Hakey , Steven J. Holmes , David V. Horak , Robert K. Leidy , William Hsioh-Lien Ma , Ronald M. Martino , Song Peng
IPC分类号： H01L21461
CPC分类号： H01L27/10864 , H01L21/0332 , H01L21/0334 , Y10S438/942
摘要： A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.
摘要翻译： 公开了一种在光刻工艺中形成正方形形状图像的方法，其中沿第一方向延伸的第一多条线被限定在第一，通常是牺牲层中，然后定义第二抗蚀剂，其中线以相交图案 到第一层的那些，从而在第一和第二层交叉的任何地方以及在线之间的开放区域中产生拐角图像。 提出了用于显影方形交叉区域和由开口限定的方角区域的方法。 此外，公开了一种光掩模，其中使用双曝光工艺独立地对角形图像的长度和宽度进行图案化。
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10.发明授权Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region 失效在隔离区域中制造具有锥形间隔物的浅结的半导体器件
公开(公告)号：US5998248A
公开(公告)日：1999-12-07
申请号：US236693
申请日：1999-01-25
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L29/08 , H01L29/423 , H01L21/8238
CPC分类号： H01L29/66628 , H01L21/2257 , H01L21/28052 , H01L21/28114 , H01L29/0847 , H01L29/42376 , H01L29/665 , H01L29/66545 , Y10S438/978
摘要： A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions and polysilicon gate regions.
摘要翻译： 通过提供具有源极和漏极区域和多晶硅栅极区域的半导体衬底来提供具有浅结的半导体器件; 在源极和漏极区上沉积选择性硅; 在形成浅结的源极和漏极区域中提供掺杂剂; 在所述栅极区域的侧壁上形成第一绝缘间隔物; 在所述第一绝缘间隔物上形成第二绝缘侧壁间隔物; 并且将源极和漏极区域和多晶硅栅极区域的顶表面硅化。
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