公开(公告)号：US6051487A

公开(公告)日：2000-04-18

申请号：US993612

申请日：1997-12-18

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Mark C. Gilmer ,  Robert Paiz

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Mark C. Gilmer ,  Robert Paiz

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L21/3205

CPC分类号： H01L21/28194 ,  H01L21/28238 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66537

摘要： A semiconductor device is formed by forming a sacrificial plug over a substrate and forming active regions in the substrate adjacent the sacrificial plug. A film is then formed over portions of the substrate adjacent the sacrificial plug. The sacrificial plug is then selectively removed leaving an opening in the film, and a gate electrode is formed in the opening. The sacrificial plug can be formed from several materials including, for example, polysilicon and nitrogen-bearing species such as nitride. The gate electrode may, for example, be formed from temperature-sensitive metals such as copper since the gate electrode may be formed subsequent to high temperature steps of the fabrication, such as a source drain anneal, for example.

摘要翻译： 半导体器件通过在衬底上形成牺牲插塞并在邻近牺牲插塞的衬底中形成有源区而形成。 然后在与牺牲插塞相邻的衬底的部分上形成膜。 然后选择性地去除牺牲塞，在膜中留下开口，并且在开口中形成栅电极。 牺牲塞可以由几种材料形成，包括例如多晶硅和含氮物质如氮化物。 栅电极可以例如由诸如铜的温度敏感金属形成，因为栅电极可以在制造的高温步骤（例如源极漏极退火）之后形成。

公开(公告)号：US6057584A

公开(公告)日：2000-05-02

申请号：US994302

申请日：1997-12-19

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  H. Jim Fulford ,  Jack C. Lee

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  H. Jim Fulford ,  Jack C. Lee

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583 ,  H01L21/2822 ,  H01L21/28229

摘要： A semiconductor device having a gate insulating tri-layer includes a substrate, a nitrogen-containing layer disposed on the substrate, a first dielectric layer disposed over the nitrogen containing layer, a second dielectric layer disposed over the first dielectric layer, and a gate electrode disposed over the second dielectric layer. One of the first and second dielectric layers is formed using an oxide having a dielectric constant ranging from 4 to 100 and the other of the first and second dielectric layers is formed using an oxide having a higher dielectric constant ranging from 10 to 10,000.

摘要翻译： 具有栅绝缘三层的半导体器件包括衬底，设置在衬底上的含氮层，设置在含氮层上的第一介电层，设置在第一介电层上的第二电介质层和栅电极 设置在第二电介质层上。 使用介电常数为4〜100的氧化物形成第一和第二电介质层中的一个，并且使用介电常数介于10〜10000的氧化物形成第一和第二电介质层中的另一个。

公开(公告)号：US06261909B1

公开(公告)日：2001-07-17

申请号：US09225389

申请日：1999-01-05

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L29/66613 ,  H01L29/7834

摘要： The present invention is directed to a method of forming a transistor having very shallow junctions and a reduced channel length, and a transistor incorporating same. In general, the method comprises forming a first process layer above a semiconducting substrate, and forming a second process layer comprised of an oxidation resistant material above the first process layer. The method continues with the formation of an opening in the first and second process layers and oxidation of the substrate lying within the opening to form a third process layer. Next, a second opening is formed in the third process layer, and a plurality of sidewall spacers are formed in the second opening. The method concludes with the formation of a gate dielectric above the substrate and between the sidewall spacers, the formation of a gate conductor above the gate dielectric, and the formation of a plurality of source and drain regions in the substrate. The transistor is comprised of a recess formed in the substrate, a gate dielectric positioned above the substrate lying within the recess, the interface between said gate dielectric and said substrate being positioned beneath the surface of said substrate. The transistor further comprises a gate conductor positioned above the gate dielectric, a plurality of sidewall spacers positioned adjacent the gate conductor, and a plurality of source/drain regions formed in the substrate.

摘要翻译： 本发明涉及一种形成具有非常浅的结和减小的沟道长度的晶体管的方法，以及并入其的晶体管。 通常，该方法包括在半导体衬底上形成第一工艺层，以及形成由第一工艺层上方的耐氧化材料构成的第二工艺层。 该方法继续在第一和第二处理层中形成开口并且位于开口内的基板的氧化以形成第三处理层。 接下来，在第三处理层中形成第二开口，并且在第二开口中形成多个侧壁间隔物。 该方法的结论是在衬底之上和侧壁间隔物之间​​形成栅极电介质，在栅极电介质上形成栅极导体，以及在衬底中形成多个源极和漏极区域。 晶体管由形成在基板中的凹槽，位于凹槽内的基板上方的栅介质构成，所述栅极电介质和所述基板之间的界面位于所述基板的表面之下。 晶体管还包括位于栅极电介质上方的栅极导体，邻近栅极导体定位的多个侧壁间隔件，以及形成在基板中的多个源极/漏极区域。

公开(公告)号：US06245638B1

公开(公告)日：2001-06-12

申请号：US09128235

申请日：1998-08-03

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  Y10S148/05

摘要： Semiconductor device fabrication techniques which integrate the formation of trench isolation areas and gate insulating layers are provided. The fabrication techniques include forming one or more sacrificial layers, such as nitrided oxide layers, over regions of the substrate adjacent to a trench isolation region. The sacrificial layers are then removed prior to gate insulating layer formation. The formation of the sacrificial layers improves the trench structure and also improves the substrate surface for the subsequent formation of the gate insulating layer and gate electrode.

摘要翻译： 提供集成沟槽隔离区域和栅极绝缘层的形成的半导体器件制造技术。 制造技术包括在与沟槽隔离区相邻的衬底的区域上形成一个或多个牺牲层，例如氮化氧化物层。 然后在形成栅极绝缘层之前去除牺牲层。 牺牲层的形成改善了沟槽结构，并且还改善了衬底表面，以便随后形成栅极绝缘层和栅电极。

公开(公告)号：US06207995B1

公开(公告)日：2001-03-27

申请号：US09255917

申请日：1999-02-23

申请人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford

发明人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford

IPC分类号： H01L2976

CPC分类号： H01L21/28194 ,  H01L29/42368 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/78391

摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate insulating layer on the substrate with a first outwardly tapered sidewall and a second outwardly tapered sidewall. A gate electrode is formed on the gate insulating layer. A first source/drain region and a second source/drain region are formed in the substrate by implanting ions into the substrate, wherein a first portion of the ions passes through the first sidewall and a second portion of the ions passes through the second sidewall. The method provides for incorporation of spacer-like structure into a gate dielectric layer. Conventional spacer fabrication may be eliminated and graded source/drain regions established with a single implant.

摘要翻译： 提供集成电路及其制造晶体管的方法。 在一个方面，该方法包括以下步骤：在衬底上形成具有第一向外锥形侧壁和第二向外渐缩侧壁的栅极绝缘层。 在栅极绝缘层上形成栅电极。 通过将离子注入衬底而在衬底中形成第一源/漏区和第二源极/漏极区，其中离子的第一部分穿过第一侧壁，并且离子的第二部分通过第二侧壁。 该方法提供了将间隔物结构结合到栅介质层中。 可以消除传统的间隔物制造，并用单个植入物建立分级的源极/漏极区域。

公开(公告)号：US06204148B1

公开(公告)日：2001-03-20

申请号：US09329843

申请日：1999-06-11

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

IPC分类号： H01L2176

CPC分类号： H01L29/66583

摘要： A partially formed semiconductor device includes a substrate, a first layer, a layer of polysilicon, and a grown layer of polysilicon. The first layer is positioned above at least a portion of the substrate. The layer of polysilicon is positioned above at least a portion of the first layer and has a first opening formed therein. The first opening has a first width that is defined by a plurality of sidewalls. The grown layer of polysilicon is positioned adjacent at least the plurality of sidewalls and the grown layer of polysilicon defines a second opening. The second opening has a second width with the second width being less than the first width. A method for partially forming a semiconductor device includes forming a process layer above at least a portion of a substrate. A layer of polysilicon is formed above at least a portion of the process layer. An opening is formed in the layer of polysilicon, and the opening has a first width that is defined by a plurality of sidewalls. The first width of the opening is reduced to a second width by growing a layer of polysilicon adjacent at least a portion of the sidewalls of the opening.

摘要翻译： 部分形成的半导体器件包括衬底，第一层，多晶硅层和生长的多晶硅层。 第一层位于衬底的至少一部分上方。 多晶硅层位于第一层的至少一部分的上方，并且其中形成有第一开口。 第一开口具有由多个侧壁限定的第一宽度。 多晶硅生长层位于至少多个侧壁附近，并且生长的多晶硅层限定第二开口。 第二开口具有第二宽度，第二宽度小于第一宽度。 部分形成半导体器件的方法包括在衬底的至少一部分上方形成工艺层。 在工艺层的至少一部分上方形成多晶硅层。 在多晶硅层中形成开口，并且开口具有由多个侧壁限定的第一宽度。 通过在开口的侧壁的至少一部分附近生长一层多晶硅，将开口的第一宽度减小到第二宽度。

公开(公告)号：US6107150A

公开(公告)日：2000-08-22

申请号：US148095

申请日：1998-09-04

申请人： Mark I. Gardner ,  H. Jim Fulford

发明人： Mark I. Gardner ,  H. Jim Fulford

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/26506 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/518 ,  Y10T408/89 ,  Y10T408/9065

摘要： The present invention is directed to a semiconductor device having an ultra thin gate oxide and a method for making same. The method is comprised of implanting nitrogen into a region of a semiconducting substrate, and forming a gate dielectric above the region in the substrate. The method further comprises forming a gate conductor above the gate dielectric and forming at least one source/drain region. The present invention is also directed to a transistor having a gate dielectric positioned above a surface of a semiconducting substrate, the gate dielectric being comprised of a nitrogen bearing oxide having a nitrogen concentration ranging from approximately 4-8%. The transistor further comprises a gate conductor positioned above the gate dielectric and at least one source/drain region.

摘要翻译： 本发明涉及一种具有超薄栅极氧化物的半导体器件及其制造方法。 该方法包括将氮注入到半导体衬底的区域中，以及在衬底中的区域的上方形成栅极电介质。 该方法还包括在栅极电介质上方形成栅极导体，并形成至少一个源极/漏极区域。 本发明还涉及一种晶体管，其具有位于半导体衬底的表面上方的栅极电介质，该栅极电介质由具有约4-8％的氮浓度的含氮氧化物构成。 晶体管还包括位于栅极介质上方的栅极导体和至少一个源极/漏极区域。

公开(公告)号：US6090676A

公开(公告)日：2000-07-18

申请号：US149210

申请日：1998-09-08

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423

CPC分类号： H01L29/66583 ,  H01L21/2652 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66598

摘要： A process for making a high performance MOSFET with a scaled gate electrode thickness. In one embodiment, the process comprises first providing a substrate. A gate dielectric layer is formed on the substrate, and a gate electrode is formed on the gate dielectric layer. A middle portion of the gate electrode has a first height, and side portions of the gate electrode have heights that are less than the first height. A dopant species is implanted at a first energy level and at a first concentration, whereby lightly doped drain regions are formed in the substrate below the side portions of the gate electrode.

摘要翻译： 制造具有定标栅极电极厚度的高性能MOSFET的工艺。 在一个实施例中，该方法包括首先提供衬底。 在基板上形成栅介电层，在栅介质层上形成栅电极。 栅电极的中间部分具有第一高度，并且栅电极的侧部具有小于第一高度的高度。 以第一能级和第一浓度注入掺杂剂物质，由此在栅电极的侧部下方的衬底中形成轻掺杂漏极区。

公开(公告)号：US5977602A

公开(公告)日：1999-11-02

申请号：US995076

申请日：1997-12-19

申请人： Mark I. Gardner ,  H. Jim Fulford

发明人： Mark I. Gardner ,  H. Jim Fulford

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/54

CPC分类号： H01L21/76243 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/6659 ,  H01L29/66772 ,  H01L21/26506 ,  H01L21/26533

摘要： A semiconductor device having an oxygen-rich punchthrough region under the channel region, and a process for fabricating such a device are disclosed. In accordance with one embodiment, a semiconductor device is formed by forming an oxygen-rich punchthrough region in a substrate, and forming a channel region over the oxygen-rich punchthrough region. The use of an oxygen-rich punchthrough region may, for example, inhibit the diffusion of dopants used in forming the channel region.

摘要翻译： 公开了一种在通道区域下方具有富氧穿透区域的半导体器件及其制造方法。 根据一个实施例，通过在衬底中形成富氧穿透区域并在富氧穿透区域上形成沟道区域形成半导体器件。 例如，使用富氧穿透区域可以抑制在形成沟道区域中使用的掺杂剂的扩散。

公开(公告)号：US5920103A

公开(公告)日：1999-07-06

申请号：US879508

申请日：1997-06-20

申请人： H. Jim Fulford ,  Mark I. Gardner

发明人： H. Jim Fulford ,  Mark I. Gardner

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7835 ,  H01L21/28176 ,  H01L29/6656 ,  H01L29/66659 ,  H01L21/28194 ,  H01L29/518

摘要： A transistor fabrication process is provided which derives a benefit from having an asymmetrical LDD structure. A gate oxide layer is grown across a silicon-based substrate. A polysilicon layer is then deposited across the gate oxide layer. Portions of the polysilicon layer and the oxide layer are removed to form a gate conductor and gate oxide, thereby exposing source-side and drain-side junctions within the substrate. The source-side and drain-side junctions are implanted with a dopant to form LDD areas therein. The source-side junction may then be exclusively implanted to form a heavily doped source region in the source-side junction. An etch stop material may be formed upon opposed sidewall surfaces of the gate conductor, the upper surface of the gate conductor, and the source-side and drain-side junctions. Spacers may then be formed laterally adjacent the etch stop material located upon sidewall surfaces of the gate conductor. The unmasked portions of the source-side and drain-side junctions are heavily doped, resulting in source and drain regions that are aligned to the exposed lateral edges of the spacers. The drain-side spacer is removed and barrier atoms are forwarded through the exposed etch stop material and into a substrate/gate oxide interface region near the drain junction. The barrier atoms help reduce hot electron effects by blocking diffusion avenues of carriers (holes or electrons) from the drain-side junction into the gate oxide.

摘要翻译： 提供了一种晶体管制造工艺，其从具有不对称的LDD结构中获益。 栅极氧化物层跨越硅基衬底生长。 然后在栅极氧化物层上沉积多晶硅层。 去除多晶硅层和氧化物层的部分以形成栅极导体和栅极氧化物，从而暴露衬底内的源极侧和漏极侧结。 用掺杂剂注入源极侧和漏极侧结以在其中形成LDD区域。 然后，源极侧结可以被独占地注入以在源极侧结中形成重掺杂源极区。 蚀刻停止材料可以形成在栅极导体的相对的侧壁表面，栅极导体的上表面以及源极侧和漏极侧结。 然后可以在位于栅极导体的侧壁表面上的蚀刻停止材料的横向邻近地形成间隔。 源侧和漏极侧结的未屏蔽部分被重掺杂，导致源极和漏极区域与间隔物的暴露的侧向边缘对准。 去除漏极侧隔离物，并且阻挡原子通过暴露的蚀刻停止材料并且进入到漏极结附近的衬底/栅极氧化物界面区域中。 阻挡原子有助于通过阻止载流子（空穴或电子）从漏极侧结到扩散通道到栅极氧化物中来减少热电子效应。