公开(公告)号：US5592010A

公开(公告)日：1997-01-07

申请号：US343359

申请日：1994-11-22

申请人： Masakazu Kakumu ,  Kazutaka Nogami ,  Yuki Satoh

发明人： Masakazu Kakumu ,  Kazutaka Nogami ,  Yuki Satoh

IPC分类号： G05F3/20 ,  H01L29/76

CPC分类号： G05F3/205

摘要： A semiconductor device comprising a main circuit having a p-channel MOSFET formed on the surface off the substrate and an n-channel MOSFET formed on the p-type well region which is formed on the n-type Si substrate chip), an input/output (I/O) circuit formed on the substrate, and a substrate bias generating circuit formed on the substrate, characterized by controlling the substrate bias generating circuit via the I/O circuit, and varying a bias supplied to the substrate and the p-type well region, in accordance with the operation mode of the main circuit.

摘要翻译： 一种半导体器件，包括形成在衬底表面上的p沟道MOSFET的主电路和形成在形成于n型Si衬底芯片上的p型阱区上的n沟道MOSFET），输入/ 形成在基板上的输出（I / O）电路和形成在基板上的基板偏压产生电路，其特征在于，经由I / O电路控制基板偏压产生电路，并且改变提供给基板和p- 根据主电路的工作模式，键入井区。

公开(公告)号：US5073813A

公开(公告)日：1991-12-17

申请号：US557716

申请日：1990-07-26

申请人： Shigeru Morita ,  Kikuo Yamabe ,  Masakazu Kakumu

发明人： Shigeru Morita ,  Kikuo Yamabe ,  Masakazu Kakumu

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/76224 ,  H01L21/768

摘要： A MOS structure is formed on a silicon semiconductor substrate surface using a first gate electrode film made of polysilicon, an element isolation groove reaching the inside of the silicon semiconductor substrate is formed, and an insulating film is filled in the groove. In addition, a second gate electrode film made of a refractory metal such as molybdenum silicide is formed to be connected to the first gate electrode film, and the first and second gate electrode films are simultaneously removed to form a MOS gate electrode and a wiring layer.

摘要翻译： 使用由多晶硅制成的第一栅极电极膜，在硅半导体衬底表面上形成MOS结构，形成到硅半导体衬底内部的元件隔离沟，并且将绝缘膜填充到沟槽中。 此外，形成由诸如硅化钼的难熔金属制成的第二栅极电极膜，以连接到第一栅极电极膜，并且同时去除第一和第二栅极电极膜以形成MOS栅电极和布线层 。

公开(公告)号：US5756365A

公开(公告)日：1998-05-26

申请号：US719334

申请日：1996-09-25

申请人： Masakazu Kakumu

发明人： Masakazu Kakumu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/66575 ,  H01L21/28105 ,  H01L21/823807 ,  H01L29/4983 ,  H01L29/6659 ,  H01L29/7836 ,  Y10S257/90

摘要： In a semiconductor device, an n.sup.+ -type polysilicon layer is formed on a substrate through a gate oxide layer. A p.sup.+ -type source or drain diffusion layer is formed on both sides of an impurity layer in the substrate. The n.sup.+ -type polysilicon layer is positioned over an intermediate portion of a channel formation layer, and has an oxide layer on an upper surface thereof. The n.sup.+ -type polysilicon layer has at its side portions a p.sup.+ -type polysilicon layer to make a gate electrode together with the n.sup.+ -type polysilicon layer. The gate electrode semiconductor layer is formed on the channel formation layer through the gate insulation layer in such a manner that in a portion contacting with the gate insulation layer, the nearer the portion approaches the impurity layers of the source and drain regions, the larger the work function of the portion becomes.

摘要翻译： 在半导体器件中，通过栅极氧化物层在衬底上形成n +型多晶硅层。 在衬底的杂质层的两侧上形成p +型源极或漏极扩散层。 n +型多晶硅层位于沟道形成层的中间部分上方，并且在其上表面具有氧化物层。 n +型多晶硅层的侧部具有p +型多晶硅层，以与n +型多晶硅层一起形成栅电极。 栅极电极半导体层通过栅极绝缘层形成在沟道形成层上，使得在与栅极绝缘层接触的部分越接近源极和漏极区的杂质层的部分越大， 该部分的工作功能变成了。

公开(公告)号：US5654241A

公开(公告)日：1997-08-05

申请号：US454647

申请日：1989-12-21

申请人： Masakazu Kakumu

发明人： Masakazu Kakumu

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L21/441

CPC分类号： H01L27/11 ,  H01L21/26506 ,  H01L21/28044 ,  H01L21/28518 ,  H01L21/823835

摘要： In a method for manufacturing a semiconductor device, metal ions are doped into the surface regions of diffusion layers or a diffusion layer forming region, thereby forming metal silicide layers of low resistance on only the diffusion layers. In a further method for manufacturing a semiconductor device, metal ions are doped into the surface regions of diffusion layers or a diffusion layer forming region and the upper surface of a gate electrode. Then, the structure is subjected to a process to make a silicide, thereby forming metal silicide layers of low resistance on only the diffusion layers and the gate electrode.

摘要翻译： 在制造半导体器件的方法中，金属离子掺杂到扩散层或扩散层形成区域的表面区域中，从而在仅扩散层上形成低电阻的金属硅化物层。 在制造半导体器件的另一方法中，将金属离子掺杂到扩散层的表面区域或扩散层形成区域和栅电极的上表面。 然后，对该结构进行制造硅化物的工艺，从而仅在扩散层和栅电极上形成低电阻的金属硅化物层。

公开(公告)号：US4746625A

公开(公告)日：1988-05-24

申请号：US15037

申请日：1987-02-17

申请人： Sigeru Morita ,  Masakazu Kakumu

发明人： Sigeru Morita ,  Masakazu Kakumu

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/425 ,  H01L21/473

CPC分类号： H01L21/76216

摘要： A semiconductor manufacturing method which comprises the steps of forming a polycrystalline silicon layer on a semiconductor substrate; depositing a silicon oxide layer on the polycrystalline silicon layer; mounting an acidproof layer on the silicon oxide layer; selectively eliminating the acidproof layer deposited on a semiconductor element-isolating region by the photoetching process; selectively eliminating the silicon oxide layer with the retained acidproof layer used as a mask; ion implanting a channel stopper impurity in the semiconductor substrate through the masks formed of a photoresist coated on the acidproof layer the acidproof layer, and silicon oxide layer; eliminating the photoresist; selectively depositing a silicon layer on the exposed polycrystalline silicon; carrying out thermal oxidation with the acidproof layer used as a mask; eliminating the acidproof layer; filling an oxide in the cavities of the side walls of the semiconductor element-isolating insulation layer; and exposing by etching that portion of the semiconductor substrate which will constitute a semiconductor element region, thereby forming a thick semiconductor element-isolating layer with high precision in a narrow semiconductor element-isolating region.

摘要翻译： 一种半导体制造方法，包括以下步骤：在半导体衬底上形成多晶硅层; 在所述多晶硅层上沉积氧化硅层; 在氧化硅层上安装耐酸层; 选择性地消除通过光刻工艺沉积在半导体元件隔离区上的耐酸层; 选择性地除去用作掩模的保留的防酸层的氧化硅层; 离子通过由涂覆在耐酸层上的光致抗蚀剂形成的掩模和氧化硅层在半导体衬底中注入沟道阻挡杂质; 消除光刻胶; 在暴露的多晶硅上选择性地沉积硅层; 用作为掩模的耐酸层进行热氧化; 消除耐酸层; 在半导体元件隔离绝缘层的侧壁的空腔中填充氧化物; 通过蚀刻构成半导体元件区域的半导体基板的部分进行曝光，从而在窄半导体元件隔离区域中形成高精度的厚半导体元件隔离层。

公开(公告)号：US5489795A

公开(公告)日：1996-02-06

申请号：US317835

申请日：1994-10-04

申请人： Hisao Yoshimura ,  Takeo Maeda ,  Masakazu Kakumu

发明人： Hisao Yoshimura ,  Takeo Maeda ,  Masakazu Kakumu

IPC分类号： H01L21/74 ,  H01L21/762 ,  H01L27/092 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/743 ,  H01L21/76218 ,  H01L27/0928

摘要： A semiconductor device has a first P type well region (11) formed on an N type semiconductor substrate (10) and a second N type well region (12) formed so as to enclose the first well region. A third N type well region (13) formed on the semiconductor substrate is enclosed by a fourth P type well region (14). The first well region adjoins and is electrically connected to the fourth well region. Contact regions (15, 16) are formed on the first and third well regions to apply a bias voltage to the PN junction between the first and third well regions. An NMOS FET is formed in the first well region and a PMOS FET is formed in the third well region. The drain currents of the NMOS FET and PMOS FET are controlled by changing the reverse bias voltage applied to the two contact regions (15, 16). The depth of the first well region (11) is such that a depletion layer extending below the NMOS FET gate electrode (50) can be connected to a depletion layer formed at an interface between the first and second well regions. The depth of the third well region is such that a depletion layer extending below the gate electrode (5) of the PMOS FET can be connected to a depletion layer formed at the interface between the third and fourth well regions.

摘要翻译： 半导体器件具有形成在N型半导体衬底（10）上的第一P型阱区（11）和形成为包围第一阱区的第二N型阱区（12）。 形成在半导体衬底上的第三N型阱区（13）由第四P型阱区（14）包围。 第一阱区邻接并与第四阱区电连接。 接触区域（15,16）形成在第一和第三阱区域上，以将偏置电压施加到第一和第三阱区域之间的PN结。 在第一阱区中形成NMOS FET，在第三阱区中形成PMOS FET。 通过改变施加到两个接触区域（15,16）的反向偏置电压来控制NMOS FET和PMOS FET的漏极电流。 第一阱区（11）的深度使得在NMOS FET栅电极（50）下方延伸的耗尽层可以连接到形成在第一阱区和第二阱区之间的界面处的耗尽层。 第三阱区的深度使得在PMOS FET的栅电极（5）下方延伸的耗尽层可以连接到形成在第三阱区和第四阱区之间的界面处的耗尽层。

公开(公告)号：US5466958A

公开(公告)日：1995-11-14

申请号：US146717

申请日：1993-11-01

申请人： Masakazu Kakumu

发明人： Masakazu Kakumu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/66575 ,  H01L21/28105 ,  H01L21/823807 ,  H01L29/4983 ,  H01L29/6659 ,  H01L29/7836 ,  Y10S257/90

摘要： In a semiconductor device, an n.sup.+ polysilicon layer is formed on a substrate through a gateoxide layer. A p.sup.+ source or drain diffusion layer is formed on both sides of an impurity layer in the substrate. The silicon layer positions over an intermediate portion of a channel formation layer, and has an oxide layer on upper surface thereof. The silicon layers have their side portions a p.sup.+ type polysilicon layer to be a gate electrode together with the silicon layer. The gate electrode semiconductor layer is formed on the channel formation layer through the gate insulation layer in the manner that, in a portion contacting with the gate insulation layer, the nearer portions approaches to the impurity layers of the source and drain regions, the larger a work function increases.

摘要翻译： 在半导体器件中，通过栅极氧化物层在衬底上形成n +多晶硅层。 在衬底的杂质层的两面上形成p +源极或漏极扩散层。 硅层位于沟道形成层的中间部分上方，并且在其上表面具有氧化物层。 硅层的侧面部分是p +型多晶硅层，与硅层一起成为栅电极。 栅极电极半导体层通过栅极绝缘层形成在沟道形成层上，使得在与栅极绝缘层接触的部分中较近的部分接近源极和漏极区域的杂质层时，较大的a 工作功能增加。

公开(公告)号：US5300462A

公开(公告)日：1994-04-05

申请号：US910458

申请日：1992-07-08

申请人： Masakazu Kakumu

发明人： Masakazu Kakumu

IPC分类号： H01L21/3213 ,  C23C14/18 ,  C23C14/48 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/465 ,  C23C14/34 ,  H01L21/324

CPC分类号： C23C14/185 ,  C23C14/48 ,  H01L21/76838 ,  Y10S148/105

摘要： A method is disclosed for alloying a sputtered metal film by forming a sputtered metal film of first metal atoms over a semiconductor substrate through a first mask and implanting a first impurity of second metal atoms into the sputtered film. Then a second mask having at least one window is formed on the sputtered film by removing said first mask and a second impurity of third metal atoms is then implanted. The substrate and film are then heat treated to form a first alloy area in which the first metal atoms and the second metal atoms are mixed and a second alloy area in which the first metal atoms and the third metal atoms are mixed.

摘要翻译： 公开了一种通过在半导体衬底上通过第一掩模形成第一金属原子的溅射金属膜并将第二金属原子的第一杂质注入到溅射膜中来合金化溅射金属膜的方法。 然后通过去除所述第一掩模在溅射膜上形成具有至少一个窗口的第二掩模，然后植入第三金属原子的第二杂质。 然后对基材和膜进行热处理以形成其中第一金属原子和第二金属原子混合的第一合金区域和混合第一金属原子和第三金属原子的第二合金区域。

公开(公告)号：US5847412A

公开(公告)日：1998-12-08

申请号：US867984

申请日：1997-06-03

申请人： Masakazu Kakumu ,  Masaaki Kinugawa

发明人： Masakazu Kakumu ,  Masaaki Kinugawa

IPC分类号： H01L21/762 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/11 ,  H01L21/76202 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： A plurality of silicon insulating films are formed to separate regions to be formed with elements from each other on a silicon semiconductor substrate. Silicon layers are formed by an epitaxially growing method on the regions to be formed with the elements and the silicon insulating film. An MOS transistor is formed on the monocrystalline silicon layer formed on the regions to be formed with the elements of the silicon layer, and the polysilicon layer formed on the silicon insulating film is used as a high resistance element or doped with an impurity as a conductor line.

摘要翻译： 形成多个硅绝缘膜，以在硅半导体衬底上分离要由元件彼此形成的区域。 在由元件和硅绝缘膜形成的区域上通过外延生长方法形成硅层。 在形成有硅层的元件的区域上形成的单晶硅层上形成MOS晶体管，将形成在硅绝缘膜上的多晶硅层用作高电阻元件或掺杂杂质作为导体 线。

公开(公告)号：US5278430A

公开(公告)日：1994-01-11

申请号：US835081

申请日：1992-02-18

申请人： Masakazu Kakumu

发明人： Masakazu Kakumu

IPC分类号： H01L27/06 ,  H01L27/092 ,  H01L27/01 ,  H01L27/02 ,  H01L29/161

CPC分类号： H01L27/092 ,  H01L27/0605 ,  Y10S257/925

摘要： A complementary semiconductor device incorporating semiconductor composed of diamond. Substantially, diamond is insulative. When both III group elementary atoms and V group elementary atoms are doped into diamond, the doped regions respectively turn into p-type and n-type semiconductors. The embodiment discretely dopes both III group elementary atoms and V group elementary atoms into a layer of diamond thin film to eventually form a complementary semiconductor device. The embodiment forms wiring system inside of the diamond thin film by selectively doping either III group elementary atoms or V group elementary atoms therein without forming wiring system only on the inter-layer insulation film.

摘要翻译： 包含由金刚石组成的半导体的互补半导体器件。 实质上，钻石是绝缘的。 当III族元素原子和V族元素原子掺入金刚石时，掺杂区分别变为p型和n型半导体。 该实施方案将III族元素原子和V族元素原子离散地掺杂到金刚石薄膜层中，以最终形成互补的半导体器件。 该实施例通过在层间绝缘膜上仅选择性地掺杂III族元素原子或V族元素原子而不形成布线系统而在金刚石薄膜的内部形成布线系统。