公开(公告)号：US6111792A

公开(公告)日：2000-08-29

申请号：US267665

申请日：1999-03-15

申请人： Satoru Oku ,  Hiroyuki Kobatake ,  Masakazu Amanai ,  Kazuaki Kato ,  Masaki Kaneko

发明人： Satoru Oku ,  Hiroyuki Kobatake ,  Masakazu Amanai ,  Kazuaki Kato ,  Masaki Kaneko

IPC分类号： G11C16/06 ,  G11C8/12 ,  G11C16/02 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C8/12

摘要： Disclosed herein is a non-volatile semiconductor memory device comprising a mode signal output means for outputting a mode signal for conducting flash programming or flash erasing, a group selection signal output means for outputting a group selection signal for selecting a row decoding group, a first selection means for selecting the row decoding group controlling the word line in accordance with 10 the group selection signal, and a second selection means selecting the word line corresponding to the memory cell from a plurality of the word lines controlled by the row decoding group selected by the first selection means. In the present inventions the time required for the flash programming and the flash erasing can be reduced without the addition of a further element and the chip areas can be reduced.

摘要翻译： 这里公开了一种非易失性半导体存储器件，包括用于输出用于进行闪存编程或闪速擦除的模式信号的模式信号输出装置，用于输出用于选择行解码组的组选择信号的组选择信号输出装置，第一 选择装置，用于根据10选择组选择信号来选择控制字线的行解码组;以及第二选择装置，从由所选择的行解码组控制的多个字线中选择与存储器单元相对应的字线， 第一选择手段。 在本发明中，可以减少闪存编程和闪存擦除所需的时间，而不需要添加另外的元件，并且可以减少芯片面积。

公开(公告)号：US06084387A

公开(公告)日：2000-07-04

申请号：US243550

申请日：1999-02-03

申请人： Masaki Kaneko ,  Hiroyuki Kobatake ,  Masakazu Amanai ,  Kazuaki Kato ,  Satoru Oku

发明人： Masaki Kaneko ,  Hiroyuki Kobatake ,  Masakazu Amanai ,  Kazuaki Kato ,  Satoru Oku

IPC分类号： G11C16/06 ,  G05F1/56 ,  G11C16/30 ,  H02M3/07 ,  G05F1/40

CPC分类号： H02M3/073 ,  G11C16/30

摘要： A power source circuit for a flash memory includes a positive circuit section for generating a positive voltage source, a source follower transistor for converting the impedance of the first voltage source, a negative circuit section for generating a negative voltage source while maintaining a voltage difference between the output of the source follower transistor and the negative voltage source at a first reference potential. The positive circuit section includes a voltage compensating transistor having a threshold voltage equal to the threshold of the source follower transistor.

摘要翻译： 用于闪速存储器的电源电路包括用于产生正电压源的正电路部分，用于转换第一电压源的阻抗的源极跟随器晶体管，用于产生负电压源的负电路部分，同时保持负电压源之间的电压差 源极跟随器晶体管和负电压源的输出处于第一参考电位。 正电路部分包括具有等于源极跟随器晶体管的阈值的阈值电压的电压补偿晶体管。

公开(公告)号：US6115288A

公开(公告)日：2000-09-05

申请号：US272311

申请日：1999-03-19

申请人： Masakazu Amanai ,  Hiroyuki Kobatake ,  Satoru Oku ,  Kazuaki Kato ,  Masaki Kaneko

发明人： Masakazu Amanai ,  Hiroyuki Kobatake ,  Satoru Oku ,  Kazuaki Kato ,  Masaki Kaneko

IPC分类号： H01L21/8247 ,  G11C7/18 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06 ,  G11C5/06

CPC分类号： G11C7/18

摘要： A semiconductor memory device comprises a plurality of sub bit lines 12a and 12b to which a plurality of memory cell transistors 13a through 13h are connected. The sub bit lines are selectively connected to a main bit line 11a. The sub and main bit lines are made of metallic material.

摘要翻译： 半导体存储器件包括多个存储单元晶体管13a至13h连接的多个子位线12a和12b。 子位线选择性地连接到主位线11a。 副位和主位线由金属材料制成。

公开(公告)号：US5942808A

公开(公告)日：1999-08-24

申请号：US140651

申请日：1998-08-26

申请人： Masaki Kaneko ,  Hiroyuki Kobatake ,  Masakazu Amanai ,  Kazuaki Kato ,  Satoru Oku

发明人： Masaki Kaneko ,  Hiroyuki Kobatake ,  Masakazu Amanai ,  Kazuaki Kato ,  Satoru Oku

IPC分类号： G01R31/28 ,  G11C5/14 ,  G11C16/06 ,  G11C29/12 ,  H02J1/10

CPC分类号： G11C5/14 ,  Y10T307/305 ,  Y10T307/383 ,  Y10T307/391

摘要： A semiconductor device has a plurality of power supply circuits whose generated voltages are different from each other, and a plurality of internal circuits whose operating voltages are different from each other. The power supply circuits and the internal circuits are interconnected by power lines with respective power supply switches inserted therein. The power lines are connected to a single external terminal by respective control lines with respective external switches inserted therein. The power supply circuits and the internal circuits can be tested from the single external terminal.

摘要翻译： 半导体器件具有产生的电压彼此不同的多个电源电路和工作电压彼此不同的多个内部电路。 电源电路和内部电路通过插入其中的各个电源开关的电力线互连。 电源线通过相应的控制线连接到单个外部端子，其中插入有相应的外部开关。 电源电路和内部电路可以从单个外部端子进行测试。

公开(公告)号：US20090285036A1

公开(公告)日：2009-11-19

申请号：US12385844

申请日：2009-04-21

申请人： Hiroyuki Kobatake

发明人： Hiroyuki Kobatake

IPC分类号： G11C7/00 ,  G11C17/16 ,  G11C5/14

CPC分类号： G11C17/18 ,  G11C5/147 ,  G11C17/16

摘要： A fuse data read circuit includes a fuse data holding unit which holds fuse data, a fuse data read unit which detects fuse data, and a bias voltage generating circuit which generates a bias voltage. The fuse data read unit includes a current mirror circuit and a control circuit provided between the current mirror circuit and the fuse data holding unit. The bias voltage generating circuit applies the bias voltage to the control circuit.

摘要翻译： 熔丝数据读取电路包括保存熔丝数据的熔丝数据保持单元，检测熔丝数据的熔丝数据读取单元和产生偏置电压的偏置电压产生电路。 熔丝数据读取单元包括电流镜电路和设置在电流镜电路和熔丝数据保持单元之间的控制电路。 偏置电压产生电路将偏置电压施加到控制电路。

公开(公告)号：US6046941A

公开(公告)日：2000-04-04

申请号：US081072

申请日：1998-05-19

申请人： Hiroyuki Kobatake

发明人： Hiroyuki Kobatake

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C7/00 ,  G11C11/00

CPC分类号： G11C16/10

摘要： A semiconductor memory device of the present invention has a write circuit and bit line coupled to the write circuit. Output from the write circuit is sent to corresponding bit line by a transfer gate. During data write term, a write voltage is applied to the bit line when writing a "0" and zero volts is applied to the bit line when writing a "1". The bit line therefore is not left in a floating state when writing either a "0" or a "1". A rise in voltage potential of a bit line due to noise is prevented from occurring, thereby eliminating data writing errors.

摘要翻译： 本发明的半导体存储器件具有耦合到写入电路的写入电路和位线。 来自写入电路的输出通过传输门被发送到相应的位线。 在数据写入期间，写入“0”时写入电压被施加到位线，写入“1”时，写入电压施加到位线上。 因此，当写入“0”或“1”时，位线不会处于浮动状态。 由于噪声引起的位线电压电位的上升被防止发生，从而消除数据写入错误。

公开(公告)号：US6009027A

公开(公告)日：1999-12-28

申请号：US49057

申请日：1998-03-27

申请人： Hiroyuki Kobatake

发明人： Hiroyuki Kobatake

IPC分类号： G01R31/28 ,  G11C16/06 ,  G11C29/10 ,  G11C29/34 ,  H01L21/66 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C29/34

摘要： A checkerboard data pattern is written in a semiconductor memory with a simple arrangement. First, memory cell transistors M00-M77 are erased. A test signal TS is turned to "L," an address ax0 to "1," write signals D0, D2, D4 and D6 to "1." This causes "1" to be written in the memory cell transistors even-numbered in both the rows and columns. Then, the test signal TS is turned to "L," an X address ax0 to "0," write signals D1, D3, D5 and D7 to "1." This causes "1" to be written in the memory cell transistors odd-numbered in both the rows and columns. Thus, the checkerboard can be written with a simple arrangement by activating only the least significant bit ax0 of X addresses ax2-ax0.

摘要翻译： 棋盘格数据模式以简单的布置写在半导体存储器中。 首先，擦除存储单元晶体管M00-M77。 测试信号TS变为“L”，地址ax0至“1”，写入信号D0，D2，D4和D6为“1”。 这使得将“1”写入在行和列中均匀编号的存储单元晶体管中。 然后，将测试信号TS变为“L”，将X地址ax0设为“0”，写信号D1，D3，D5和D7变为“1”。 这将使“1”写入行和列中奇数编号的存储单元晶体管中。 因此，通过仅激活X地址ax2-ax0的最低有效位ax0，可以用简单的布置写出棋盘。

公开(公告)号：US5946229A

公开(公告)日：1999-08-31

申请号：US55701

申请日：1998-04-07

申请人： Hiroyuki Kobatake ,  Ichiro Kondo

发明人： Hiroyuki Kobatake ,  Ichiro Kondo

IPC分类号： G11C16/06 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07 ,  G11C11/34

CPC分类号： H01L27/0218

摘要： The present invention provides a semiconductor device with small space factor, which controls the application of voltages higher than a power supply voltage to internal circuits. This device includes a first transistor provided with a semiconductor substrate of one conductive type, a first region of second conductivity type formed in the semiconductor substrate, a second region of the second conductivity type formed independent of the first region, a third region of the first conductivity type formed in the first region, and a fourth region of the first conductivity type formed in the first region independent of the third region, having the first region as its back gate, and a second transistor provided with a fifth region of the first conductivity type formed in the second region and a sixth region of the first conductivity type formed in the second region independent of the fifth region, having the second region as its back gate, wherein a back gate bias voltage higher than the power supply voltage applied to the second region is applied to the first region.

摘要翻译： 本发明提供了一种具有小的空间系数的半导体器件，其控制高于内部电路的电源电压的电压的施加。 该器件包括：第一晶体管，其设置有一个导电类型的半导体衬底;形成在该半导体衬底中的第二导电类型的第一区域;第二导电类型的第二区域，与该第一区域独立地形成;第二区域， 形成在第一区域中的导电类型和第一导电类型的第四区域形成在与第三区域无关的第一区域中，具有第一区域作为其背栅极，第二晶体管设置有第一区域的第一导电性 形成在第二区域中的第一区域和第二导电类型的第六区域，其独立于第五区域形成在第二区域中，具有第二区域作为其背栅极，其中背栅极偏置电压高于施加到第二区域的电源电压 第二区域被施加到第一区域。

公开(公告)号：US5736951A

公开(公告)日：1998-04-07

申请号：US696601

申请日：1996-08-14

申请人： Hiroyuki Kobatake

发明人： Hiroyuki Kobatake

IPC分类号： H03M1/36 ,  H03M1/08

CPC分类号： H03M1/0827 ,  H03M1/365 ,  Y10T307/305 ,  Y10T307/313 ,  Y10T307/359 ,  Y10T307/383

摘要： An analog-to-digital converter comprises the following elements. A reference voltage generation circuit is provided for dividing a reference voltage into a plurality of divided reference voltages having voltage levels different from each other. A plurality of comparators are provided, each of which has a first input terminal connected to an analog input line for fetching analog signals and a second input terminal connected to the reference voltage generation circuit for fetching a corresponding one of the divided reference voltages so as to compare the analog signals with the divided reference voltage. Each of the comparators has an output terminal through which an output digital signal is outputted. The comparators are connected to any one of a plurality of pairs of different power supply lines and different ground lines, wherein the different power supply lines are separated from each other as well as the different ground lines are separated from each other so that no interference between the different power supply lines and between the different ground lines appears through any noise generated on any of the comparators. A decoder circuit is connected to the output terminals of the comparators for fetching the compared digital signals and decoding the compared digital signals.

摘要翻译： 模数转换器包括以下元件。 提供了一种参考电压产生电路，用于将参考电压分成具有彼此不同电压电平的多个划分的基准电压。 提供多个比较器，每个比较器具有连接到用于取出模拟信号的模拟输入线的第一输入端和连接到参考电压产生电路的第二输入端，用于取出对应的一个分压的参考电压，以便 将模拟信号与分频参考电压进行比较。 每个比较器具有输出端子，通过该输出端子输出输出数字信号。 比较器连接到多对不同电源线和不同接地线中的任何一个，其中不同的电源线彼此分离，并且不同的接地线彼此分离，使得 通过任何比较器上产生的任何噪声，出现不同的电源线和不同的接地线之间。 解码器电路连接到比较器的输出端，用于取出比较的数字信号并对比较的数字信号进行解码。

公开(公告)号：US5499183A

公开(公告)日：1996-03-12

申请号：US352675

申请日：1994-11-30

申请人： Hiroyuki Kobatake

发明人： Hiroyuki Kobatake

IPC分类号： H01L27/04 ,  H01L21/822 ,  H02M3/07 ,  H02M3/18 ,  G05F3/16

CPC分类号： H02M3/073

摘要： A constant voltage generating circuit comprises a charge pump circuit for generating a high voltage on a high voltage output terminal, a clamp circuit having a P-channel MOSFET having a drain and a gate interconnected to each other and a source connected to the high voltage output terminal and an anode-grounded zener diode having a cathode connected to the drain of the P-channel MOSFET. A charge detecting circuit generates a charge detection signal when the amount of electric charge having flowed through the clamp circuit reaches a predetermined value. A clock control circuit includes a RS flipflop reset by a reset signal and set by the charge detection signal, and operates to stop application of a clock signal to the charge pump circuit on the basis of an output of the RS flipflop.

摘要翻译： 恒压产生电路包括用于在高电压输出端产生高电压的电荷泵电路，具有P沟道MOSFET的钳位电路，所述P沟道MOSFET具有彼此互连的漏极和栅极，以及连接到高电压输出端的源极 端子和具有连接到P沟道MOSFET的漏极的阴极的阳极接地齐纳二极管。 当流过钳位电路的电荷量达到预定值时，充电检测电路产生电荷检测信号。 时钟控制电路包括通过复位信号进行的RS触发器复位，并由充电检测信号设定，并根据RS触发器的输出停止向电荷泵电路施加时钟信号。