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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100237346A1

    公开(公告)日：2010-09-23

    申请号：US12556102

    申请日：2009-09-09

    申请人： Hiroshi Kanno ,  Kenichi Murooka ,  Mitsuru Sato

    发明人： Hiroshi Kanno ,  Kenichi Murooka ,  Mitsuru Sato

    IPC分类号： H01L29/12 ,  H01L21/8246

    CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675

    摘要： A rectifier is formed by forming a first electrode layer, a semiconductor layer and a second electrode layer. A third electrode layer is formed between the first electrode layer and the semiconductor layer, or between the second electrode layer and the semiconductor layer.The semiconductor layer and the third electrode layer are formed as follows. First, a first layer made from amorphous silicon and including a p-type first semiconductor region and an n-type second semiconductor region is deposited. Next, a second layer made from a metal is deposited on an upper or lower layer of the first layer. The third electrode layer including a metal silicide as a material lattice-matched to polysilicon is formed by siliciding the second layer. Next, the first layer is crystallized. Subsequently, the semiconductor layer is formed by activating an impurity included in the first layer and restoring crystal imperfections included in the first layer.

    摘要翻译： 整流器通过形成第一电极层，半导体层和第二电极层而形成。 在第一电极层和半导体层之间或第二电极层和半导体层之间形成第三电极层。 半导体层和第三电极层如下形成。 首先，沉积由非晶硅制成并包括p型第一半导体区域和n型第二半导体区域的第一层。 接下来，将由金属制成的第二层沉积在第一层的上层或下层上。 通过硅化第二层来形成包括与多晶硅晶格匹配的材料的金属硅化物的第三电极层。 接下来，第一层结晶。 随后，通过激活包括在第一层中的杂质并恢复包括在第一层中的晶体缺陷来形成半导体层。

    Memory device
    6.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US08891277B2

    公开(公告)日：2014-11-18

    申请号：US13313186

    申请日：2011-12-07

    申请人： Kenichi Murooka

    发明人： Kenichi Murooka

    IPC分类号： G11C5/02 ,  G11C5/06

    CPC分类号： H01L27/2481 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/78 ,  H01L21/768 ,  H01L27/2454 ,  H01L29/66666 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/1608

    摘要： According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.

    摘要翻译： 根据一个实施例，存储器件包括第一至第三互连，存储器单元和选择器。 第一至第三互连分别沿着第一至第三方向设置。 存储单元包括形成在第三互连件的第一方向上彼此面对的两个侧表面上的可变电阻层。 选择器将第三互连与第一互连耦合。 其中一个选择器包括一个半导体层，该半导体层设置在相互连接的第三互连中的一个和第一互连中的相关一个之间，以及形成在半导体层的在第一方向上彼此相对的两个侧表面上的栅极之间的栅极绝缘膜。

    Resistance change memory
    7.
    发明授权
    Resistance change memory 有权
    电阻变化记忆

    公开(公告)号：US08498142B2

    公开(公告)日：2013-07-30

    申请号：US13072029

    申请日：2011-03-25

    申请人： Kenichi Murooka

    发明人： Kenichi Murooka

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0033 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/72

    摘要： A memory includes memory cells each includes a resistance change element and a diode, and each memory cell between one of row lines and one of column lines, a first decoder which selects one of the row lines as a selected row line, a second decoder which selects one of the column lines as a selected column line, a voltage pulse generating circuit which generates a voltage pulse, a voltage pulse shaping circuit which makes a rise time and a fall time of the voltage pulse longer, and a control circuit which applies the voltage pulse outputting from the voltage pulse shaping circuit to unselected column lines except the selected column line, and which applies a fixed potential to unselected row lines except the selected row line, in a data writing to a memory cell which is provided between the selected row line and the selected column line.

    摘要翻译： 存储器包括各自包括电阻变化元件和二极管的存储单元，以及行线和列线之一之间的每个存储单元，选择行行之一作为所选行行的第一解码器，第二解码器， 选择列线之一作为选择的列线，产生电压脉冲的电压脉冲发生电路，使电压脉冲的上升时间和下降时间更长的电压脉冲整形电路以及施加电压脉冲的控制电路 电压脉冲从电压脉冲整形电路输出到除了所选列线之外的未选择的列线，并且在设置在所选择的行之间的存储单元的数据写入中将固定电位施加到除所选行行之外的未选行行 行和所选列行。

    Non-volatile semiconductor memory device including memory cells with a variable resistor
    8.
    发明授权
    Non-volatile semiconductor memory device including memory cells with a variable resistor 有权
    包括具有可变电阻器的存储单元的非易失性半导体存储器件

    公开(公告)号：US08391048B2

    公开(公告)日：2013-03-05

    申请号：US12846198

    申请日：2010-07-29

    申请人： Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

    发明人： Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0061 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092

    摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.

    摘要翻译： 根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。 根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给 选择的存储单元。 擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

    Nonvolatile semiconductor memory device
    9.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08320157B2

    公开(公告)日：2012-11-27

    申请号：US12876637

    申请日：2010-09-07

    申请人： Reika Ichihara ,  Takayuki Tsukamoto ,  Hiroshi Kanno ,  Kenichi Murooka

    发明人： Reika Ichihara ,  Takayuki Tsukamoto ,  Hiroshi Kanno ,  Kenichi Murooka

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2213/13 ,  G11C2213/34 ,  G11C2213/72

    摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.

    摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列包括多个第一布线，与多条第一布线相交的多条第二布线，以及多个存储单元，设置在多个第一布线和第二布线的交点处，每个包括非欧姆元件和 串联连接的可变电阻元件。 控制电路选择多个存储单元中的一个，产生用于从所选存储单元擦除数据的擦除脉冲，并将擦除脉冲提供给所选存储单元。 控制电路通过在反向偏置方向上向非欧姆元件施加擦除脉冲的电压来执行数据擦除。

    Nonvolatile semiconductor memory device
    10.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08084830B2

    公开(公告)日：2011-12-27

    申请号：US12556005

    申请日：2009-09-09

    申请人： Hiroshi Kanno ,  Kenichi Murooka ,  Jun Hirota ,  Hideyuki Tabata

    发明人： Hiroshi Kanno ,  Kenichi Murooka ,  Jun Hirota ,  Hideyuki Tabata

    IPC分类号： H01L27/11

    CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/1027

    摘要： The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si1-xGex (0

    摘要翻译： 存储单元位于第一布线和第二布线之间的相应交点处。 每个存储单元具有串联连接的整流元件和可变电阻元件。 整流元件包括p型第一半导体区域和n型第二半导体区域。 第一半导体区域至少部分地由硅 - 锗混合物（Si1-xGex（0