公开(公告)号：US5445709A

公开(公告)日：1995-08-29

申请号：US154566

申请日：1993-11-19

申请人： Masayuki Kojima ,  Yoshikazu Ito ,  Kazuhsi Tomita ,  Shigeki Tozawa ,  Shunichi Iimuro ,  Masashi Arasawa ,  Eiichi Nishimura

发明人： Masayuki Kojima ,  Yoshikazu Ito ,  Kazuhsi Tomita ,  Shigeki Tozawa ,  Shunichi Iimuro ,  Masashi Arasawa ,  Eiichi Nishimura

IPC分类号： C23F4/00 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/06

CPC分类号： H01J37/32009 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32532 ,  H01J37/32541 ,  H01J37/32724 ,  H01J2237/3345

摘要： A parallel-plate plasma etching apparatus includes a susceptor electrode and a shower electrode which are arranged in a process chamber. A semiconductor wafer is placed on the susceptor electrode. A shower region defined by a plurality of process gas supply holes is formed in the shower electrode. The shower electrode is cooled by a cooling block and causes an effective electrode portion of the shower electrode to have a temperature gradient such that a temperature at the central portion of the effective electrode portion is lower than a temperature at the peripheral portion of the effective electrode portion. The diameter of the shower region is selected to be smaller than the diameter of the wafer by 5 to 25% such that degradation of planar uniformity of a degree of etching anisotropy on the wafer caused by the temperature gradient of the effective electrode portion is compensated for. The diameter of the effective electrode portion is selected to be larger than the size of a wafer by 5 to 35% such that a taper angle of a side wall to be etched formed by etching is set to be 85.degree. to 90.degree..

摘要翻译： 平行板等离子体蚀刻装置包括布置在处理室中的基座电极和淋浴电极。 将半导体晶片放置在基座电极上。 在淋浴电极中形成由多个处理气体供给孔限定的淋浴区域。 淋浴电极被冷却块冷却，使淋浴电极的有效电极部分具有温度梯度，使得有效电极部分的中心部分的温度低于有效电极周边部分的温度 一部分。 淋浴区域的直径被选择为小于晶片的直径5至25％，使得由有效电极部分的温度梯度引起的晶片上的蚀刻各向异性程度的平面均匀度的降低被补偿 。 选择有效电极部分的直径大于晶片的尺寸5至35％，使得通过蚀刻形成的待蚀刻侧壁的锥角设定为85°至90°。

公开(公告)号：US5766498A

公开(公告)日：1998-06-16

申请号：US623737

申请日：1996-03-29

申请人： Masayuki Kojima ,  Yoshikazu Ito ,  Kazushi Tomita ,  Shigeki Tozawa ,  Shunichi Iimuro ,  Masashi Arasawa ,  Eiichi Nishimura

发明人： Masayuki Kojima ,  Yoshikazu Ito ,  Kazushi Tomita ,  Shigeki Tozawa ,  Shunichi Iimuro ,  Masashi Arasawa ,  Eiichi Nishimura

IPC分类号： C23F4/00 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065

CPC分类号： H01J37/32009 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32532 ,  H01J37/32541 ,  H01J37/32724 ,  H01J2237/3345

摘要： A parallel-plate plasma etching apparatus includes a susceptor electrode and a shower electrode which are arranged in a process chamber. A semiconductor wafer is placed on the susceptor electrode. A shower region defined by a plurality of process gas supply holes is formed in the shower electrode. The shower electrode is cooled by a cooling block and causes an effective electrode portion of the shower electrode to have a temperature gradient such that a temperature at the central portion of the effective electrode portion is lower than a temperature at the peripheral portion of the effective electrode portion. The diameter of the shower region is selected to be smaller than the diameter of the wafer by 5 to 25% such that degradation of planar uniformity of a degree of etching anisotropy on the wafer caused by the temperature gradient of the effective electrode portion is compensated for. The diameter of the effective electrode portion is selected to be larger than the size of a wafer by 5 to 35% such that a taper angle of a side wall to be etched formed by etching is set to be 85.degree. to 90.degree..

公开(公告)号：US08741396B2

公开(公告)日：2014-06-03

申请号：US13060821

申请日：2009-06-30

申请人： Hiraku Ishikawa ,  Eiichi Nishimura

发明人： Hiraku Ishikawa ,  Eiichi Nishimura

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  C23C16/347 ,  C23C16/5096 ,  G03F7/091 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/3146 ,  H01L21/318

摘要： An amorphous carbon film, which has excellent etching resistance and is capable of reducing reflectance when a resist film is exposed to light, is form. A method for manufacturing a semiconductor device includes forming an object film to be etched on a wafer, supplying a process gas containing a CO gas and an N2 gas into a processing container, forming an amorphous carbon nitride film from the supplied CO gas and N2 gas, forming a silicon oxide film on the amorphous carbon nitride film, forming an ArF resist film on the silicon oxide film, patterning the ArF resist film, etching the silicon oxide film by using the ArF resist film as a mask, etching the amorphous carbon nitride film by using the silicon oxide film as a mask, and etching the object film to be etched by using the amorphous carbon nitride film as a mask.

摘要翻译： 形成了具有优异的耐蚀刻性并且当抗蚀剂膜暴露于光时能够降低反射率的无定形碳膜。 一种制造半导体器件的方法包括在晶片上形成待蚀刻的目标薄膜，将含有CO气体和N 2气体的工艺气体供给到处理容器中，从供给的CO气体和N 2气体形成无定形氮化碳膜 在无定形氮化碳膜上形成氧化硅膜，在氧化硅膜上形成ArF抗蚀剂膜，对ArF抗蚀剂膜进行构图，使用ArF抗蚀剂膜作为掩模蚀刻氧化硅膜，蚀刻无定形碳氮化物 通过使用氧化硅膜作为掩模，并且通过使用无定形氮化碳膜作为掩模来蚀刻待蚀刻的目标膜。

公开(公告)号：US08530354B2

公开(公告)日：2013-09-10

申请号：US13415363

申请日：2012-03-08

申请人： Masato Kushibiki ,  Eiichi Nishimura

发明人： Masato Kushibiki ,  Eiichi Nishimura

IPC分类号： H01L21/311

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136

摘要： The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.

摘要翻译： 本发明提供一种基板处理方法，用于处理至少包括依次堆叠的处理层，中间层和掩模层的基板。 掩模层包括被配置为暴露中间层的一部分的孔。 基板处理方法包括：材料沉积步骤，其在所述孔的侧表面上沉积材料，并且通过用沉积气体产生的等离子体蚀刻所述中间层的暴露部分来暴露所述处理层的一部分;以及蚀刻步骤 蚀刻处理层的暴露部分。

公开(公告)号：US08518828B2

公开(公告)日：2013-08-27

申请号：US12623556

申请日：2009-11-23

申请人： Tetsuo Endoh ,  Eiichi Nishimura

发明人： Tetsuo Endoh ,  Eiichi Nishimura

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/3088 ,  H01L29/66181 ,  H01L29/66787 ,  H01L29/66795

摘要： According to a disclosed semiconductor device fabrication method according to one embodiment of the present invention, a layer having a line-and-space pattern extending in one direction is etched using another layer having a line-and-space pattern extending in another direction intersecting the one direction, thereby obtaining a mask having two-dimensionally arranged dots. An underlying layer is etched using the mask, thereby providing two-dimensionally arranged pillars.

摘要翻译： 根据本发明的一个实施例公开的半导体器件制造方法，使用具有在与另一方向相交的另一个方向上延伸的线间距图案的另一层蚀刻具有沿一个方向延伸的线间距图案的层 从而获得具有二维排列的点的掩模。 使用掩模蚀刻下层，由此提供二维布置的柱。

公开(公告)号：US08491804B2

公开(公告)日：2013-07-23

申请号：US12721962

申请日：2010-03-11

申请人： Masato Kushibiki ,  Eiichi Nishimura

发明人： Masato Kushibiki ,  Eiichi Nishimura

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/311

CPC分类号： H01L21/0273 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144

摘要： A method of processing a substrate having a processing target layer and an organic film serving as a mask layer includes a mineralizing process of mineralizing the organic film. The mineralizing process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto a surface of the organic film; and an oxidation process for oxidizing the adsorbed silicon-containing gas to be converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.

摘要翻译： 处理具有加工对象层和作为掩模层的有机膜的基板的处理方法包括使有机膜成矿化的矿化工序。 矿化方法包括使含硅气体吸附在有机膜的表面上的吸附方法; 以及用于氧化被吸收的待转化为氧化硅膜的含硅气体的氧化工艺。 使用一价氨基硅烷作为含硅气体。

公开(公告)号：US20120214315A1

公开(公告)日：2012-08-23

申请号：US13400247

申请日：2012-02-20

申请人： Eiichi Nishimura ,  Takashi Sone ,  Fumiko Yamashita

发明人： Eiichi Nishimura ,  Takashi Sone ,  Fumiko Yamashita

IPC分类号： H01L21/3065

CPC分类号： H01L21/32137

摘要： In a substrate processing method, a polysilicon layer 38 on a wafer W is etched with a bromine cation 45a and a bromine radical 45b in plasma generated from a processing gas containing a hydrogen bromide gas, an oxygen gas, and a nitrogen trifluoride gas, and then, is ashed with an oxygen radical 46 and a nitrogen radical 47 in plasma generated from a processing gas containing an oxygen gas and a nitrogen gas. Thereafter, the polysilicon layer 38 is etched with a fluorine cation 48a and a fluorine radical 48b in plasma generated from a processing gas containing an argon gas and a nitrogen trifluoride gas. While the polysilicon layer 38 is ashed, an oxidation process is performed on a silicon bromide generated by etching the polysilicon layer 38 with the bromine cation 45a.

摘要翻译： 在基板处理方法中，用含有溴化氢气体，氧气和三氟化氮气体的处理气体产生的等离子体中的溴阳离子45a和溴根45b蚀刻晶片W上的多晶硅层38， 然后，由含有氧气和氮气的处理气体产生的等离子体中的氧自由基46和氮根47被灰化。 此后，用含有氩气和三氟化氮气体的处理气体产生的等离子体中的氟阳离子48a和氟根48b进行蚀刻。 当多晶硅层38灰化时，对通过用溴阳离子45a蚀刻多晶硅层38产生的溴化硅进行氧化处理。

公开(公告)号：US08132580B2

公开(公告)日：2012-03-13

申请号：US12057807

申请日：2008-03-28

申请人： Tsuyoshi Moriya ,  Tadashi Onishi ,  Ryo Nonaka ,  Eiichi Nishimura

发明人： Tsuyoshi Moriya ,  Tadashi Onishi ,  Ryo Nonaka ,  Eiichi Nishimura

IPC分类号： B08B3/00

CPC分类号： H01L21/67051 ,  H01L21/6708

摘要： A substrate processing system that enables foreign matter adhered to a rear surface or a periphery of a substrate to be completely removed. A substrate processing apparatus performs predetermined processing on the substrate. A substrate cleaning apparatus cleans the substrate at least one of before and after the predetermined processing. A jetting apparatus jets a cleaning substance in two phases of a gas phase and a liquid phase and a high-temperature gas towards the rear surface or the periphery of the substrate.

摘要翻译： 能够完全除去附着在基板的背面或周围的异物的基板处理系统。 基板处理装置对基板进行规定的处理。 基板清洁装置在预定处理之前和之后清洁基板。 喷射装置将气相和液相以及高温气体的两相中的清洗物质喷射到基板的后表面或周边。

公开(公告)号：US08124536B2

公开(公告)日：2012-02-28

申请号：US11946289

申请日：2007-11-28

申请人： Eiichi Nishimura

发明人： Eiichi Nishimura

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31116 ,  H01L21/67069 ,  H01L28/91

摘要： A method for manufacturing a capacitor electrode by removing a silicon oxide film on a surface of a substrate, including: transforming the silicon oxide film into a reaction product by supplying a gas containing a halogen element to chemically react with the silicon oxide film while controlling temperature of the substrate to a first process temperature; and removing the silicon oxide film transformed to the reaction product while controlling the temperature of the substrate to a second process temperature higher than the first process temperature. The silicon oxide film is a BPSG film.

摘要翻译： 一种通过去除衬底表面上的氧化硅膜来制造电容器电极的方法，包括：通过提供含有卤素元素的气体将氧化硅膜转化为反应产物，以与氧化硅膜发生化学反应同时控制温度 的基底到第一工艺温度; 以及在将基板的温度控制到高于第一处理温度的第二处理温度的同时除去转化为反应产物的氧化硅膜。 氧化硅膜是BPSG膜。

公开(公告)号：US20110065280A1

公开(公告)日：2011-03-17

申请号：US12852543

申请日：2010-08-09

申请人： Shigeru Nakajima ,  Kazuhide Hasebe ,  Hidetami Yaegashi ,  Eiichi Nishimura

发明人： Shigeru Nakajima ,  Kazuhide Hasebe ,  Hidetami Yaegashi ,  Eiichi Nishimura

IPC分类号： H01L21/306

CPC分类号： H01L21/31144 ,  C23C16/26 ,  C23C16/34 ,  C23C16/45542 ,  H01J37/32082 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/32135

摘要： The method includes a film-forming process which forms a carbon film, to isotropically coat a surface of a silicon film pattern in which a first line portion formed of a silicon film that is formed on a target etching film on a substrate is arranged, an etchback process which etches back the carbon film such that the carbon film is removed from an upper portion of the first line portion and remains as a side wall portion of the first line portion, and a silicon film removing process which forms a mask pattern in which the side wall portion is arranged, by removing the first line portion.

摘要翻译： 该方法包括一个形成碳膜的成膜方法，以均匀地涂覆硅衬底上形成在靶蚀刻膜上的由硅膜形成的第一线部分的硅膜图案的表面， 回蚀处理，其蚀刻碳膜，使得碳膜从第一线部分的上部被去除并保留为第一线部分的侧壁部分，以及硅膜去除工艺，其形成掩模图案，其中 通过移除第一线部分来布置侧壁部分。