公开(公告)号：US5372615A

公开(公告)日：1994-12-13

申请号：US138261

申请日：1993-10-20

申请人： Masayuki Mizuno ,  Katsuji Yamanaka ,  Satosi Inatomi ,  Kenji Namba

发明人： Masayuki Mizuno ,  Katsuji Yamanaka ,  Satosi Inatomi ,  Kenji Namba

IPC分类号： A01G1/04 ,  C12M1/12 ,  C12M1/24

CPC分类号： A01G1/046

摘要： A bin cap for mushroom culture bins for cultivating mushrooms such as shiitake (Lentinus edodes (Berk.) Sing.), Lyophyllum shimeji (Kawam.) Hongo, and the like which includes a housing part 2 including a space S internally for ventilation and having windows 2w for ventilation with a broader open area than the open area of bin mouth Bo, breathable filter part 3 blocking window 2w, and fitting part 4 being installed at the under surface 2d of housing part 2 and being attached to or detached from bin mouth Bo. Thereby, the ventilation is secured and the exhaust of carbon dioxide is promoted.

摘要翻译： 用于培养诸如香菇（香菇（Berk。）Sing）等蘑菇的蘑菇培养箱的箱盖，包括具有内部用于通风的空间S的壳体部分2，并且具有用于通风的壳体部分2， 窗口2w通风比开口区域更大的开口区域Bo，透气过滤器部分3阻挡窗2w，以及装配部分4安装在壳体部分2的下表面2d处并且被附接到箱口或从箱口拆下 博。 由此，能够确保通气，促进二氧化碳的排出。

公开(公告)号：US5372616A

公开(公告)日：1994-12-13

申请号：US138265

申请日：1993-10-20

申请人： Masayuki Mizuno ,  Katsuji Yamanaka ,  Satosi Inatomi ,  Kenji Namba

发明人： Masayuki Mizuno ,  Katsuji Yamanaka ,  Satosi Inatomi ,  Kenji Namba

IPC分类号： A01G1/04 ,  C12M1/24 ,  C12M1/22 ,  C12M1/12

CPC分类号： A01G1/046

摘要： A bin for mushroom culture for cultivating mushrooms such as shiitake that comprises upper half bin 2 and lower half bin 3 so arranged as to be able to elongate and contract by sliding upward and downward when fitted. Fitting part C of upper half bin 2 and lower half bin 3 is so arranged as to form a ventilating route F connecting the inside and outside at an elongated position P2 compared with the most contracted position P1. Thereby, ventilation is performed through ventilating route F and carbon dioxide, which is heavier than air, is exhausted.

摘要翻译： 用于培养诸如包括上半仓2和下半仓3的蘑菇的蘑菇箱，其布置成能够在安装时向上和向下滑动而伸长和收缩。 上半部分2和下半部分3的安装部分C被布置成形成一个与最大收缩位置P1相比在细长位置P2连接内部和外部的通风路径F. 因此，通风通路F进行通气，比空气重的二氧化碳排气。

公开(公告)号：US08862934B2

公开(公告)日：2014-10-14

申请号：US13510621

申请日：2010-11-26

申请人： Yoshio Kameda ,  Masayuki Mizuno

发明人： Yoshio Kameda ,  Masayuki Mizuno

IPC分类号： G06F11/00 ,  G06F11/22 ,  G06F11/07 ,  G06F11/16

CPC分类号： G06F11/1658 ,  G06F11/0793 ,  G06F11/1629 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1687 ,  G06F11/2236

摘要： A redundant computing system is composed of two systems: a first arithmetic processing unit (A-system) and a second arithmetic processing unit (B-system) having the same functions. A diagnosis control unit performs diagnosis of one system while the other system is performing arithmetic processing operation. The diagnosis control unit controls the input to the first and second arithmetic processing units by way of an input control unit according to the diagnosis operation, and an output control unit controls the output from the first and second arithmetic processing units according to the diagnosis result. After termination of the diagnosis, a value is copied from a storage unit of the system which has not been diagnosed to a storage unit of the system which has been diagnosed, and the redundant computing system resumes the redundant operation.

摘要翻译： 冗余计算系统由具有相同功能的第一算术处理单元（A系统）和第二算术处理单元（B系统）组成。 诊断控制单元执行一个系统的诊断，而另一个系统执行算术处理操作。 诊断控制单元根据诊断操作通过输入控制单元控制对第一和第二算术处理单元的输入，并且输出控制单元根据诊断结果控制来自第一和第二算术处理单元的输出。 在诊断结束后，从尚未被诊断的系统的存储单元复制到被诊断的系统的存储单元，并且冗余计算系统恢复冗余操作。

公开(公告)号：US08635040B2

公开(公告)日：2014-01-21

申请号：US12519837

申请日：2007-12-19

申请人： Koichi Nose ,  Masayuki Mizuno ,  Atsufumi Shibayama

发明人： Koichi Nose ,  Masayuki Mizuno ,  Atsufumi Shibayama

IPC分类号： G01R13/02

CPC分类号： G01R31/31937 ,  G01R31/31708 ,  G01R31/31726

摘要： A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.

摘要翻译： 一种信号测量装置，包括测量与测量的驱动时钟信号同步的测量对象的一组或多组测量单元，并将测量结果作为第一数据输出，以及定时识别单元， 根据测量开始命令，将与每个周期不同的值作为与具有规定周期和速度低于驱动时钟信号的参考信号同步的第二数据输出; 以及与所述驱动时钟信号同步地收集并依次存储所述第一数据和所述第二数据作为一组的存储单元。

公开(公告)号：US08444316B2

公开(公告)日：2013-05-21

申请号：US12746947

申请日：2008-11-27

申请人： Eisuke Saneyoshi ,  Koichi Nose ,  Mikihiro Kajita ,  Masayuki Mizuno

发明人： Eisuke Saneyoshi ,  Koichi Nose ,  Mikihiro Kajita ,  Masayuki Mizuno

IPC分类号： G01K13/00

CPC分类号： G01K7/01 ,  G01K2219/00

摘要： Current reading means detects an output current of a current source whose output current varies with a variation in temperature and outputs a value proportional to the output current. The temperature of the current source corresponding to the output value of the current reading means which is proportional to the output current of the current source is measured, and a parameter for converting the output value to temperature information is determined from the output value of the current reading means and the measured value of the temperature of the current source corresponding to the output value. The output value of the current reading means is converted to the temperature information using the determined parameter.

摘要翻译： 电流读取装置检测输出电流随温度变化而变化的电流源的输出电流，并输出与输出电流成比例的值。 测量与电流读取装置的输出值对应的电流源的温度，其与电流源的输出电流成比例，并且根据电流的输出值确定将输出值转换为温度信息的参数 读数手段和对应于输出值的电流源的温度测量值。 使用所确定的参数将电流读取装置的输出值转换为温度信息。

公开(公告)号：US08441277B2

公开(公告)日：2013-05-14

申请号：US12810877

申请日：2008-12-16

申请人： Koichiro Noguchi ,  Yoshio Kameda ,  Koichi Nose ,  Masayuki Mizuno ,  Toshinobu Ono

发明人： Koichiro Noguchi ,  Yoshio Kameda ,  Koichi Nose ,  Masayuki Mizuno ,  Toshinobu Ono

IPC分类号： G01R31/26

CPC分类号： G01R31/31908

摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.

摘要翻译： 提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。 半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为 由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。

公开(公告)号：US08072253B2

公开(公告)日：2011-12-06

申请号：US12440967

申请日：2007-09-11

申请人： Shunichi Kaeriyama ,  Masayuki Mizuno

发明人： Shunichi Kaeriyama ,  Masayuki Mizuno

IPC分类号： H03H11/16

CPC分类号： H03L7/0995 ,  G06F1/08 ,  H03K5/13 ,  H03K5/133 ,  H03K5/1565 ,  H03K2005/00052 ,  H03K2005/00058 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/0996 ,  H03L7/0998 ,  H04L7/0337

摘要： Disclosed is a clock adjusting circuit comprising a phase shifter that receives a clock signal and variably shifts, based on a control signal, respective timing phases of a rising edge and a falling edge of the clock signal; and a control circuit that supplies the control signal to the phase shifter circuit before each edge is output; wherein the clock signal, in which at least one of a period, a duty ratio, jitter and skew/delay of the input clock signal is changed over an arbitrary number of clock cycles, is output.

摘要翻译： 公开了一种时钟调节电路，包括：移相器，其接收时钟信号，并且基于控制信号可变地移位时钟信号的上升沿和下降沿的相应定时相位; 以及控制电路，其在每个边缘被输出之前将所述控制信号提供给所述移相器电路; 其中输出时钟信号，其中输入时钟信号的周期，占空比，抖动和偏移/延迟中的至少一个在任意数量的时钟周期上改变。

公开(公告)号：US07908538B2

公开(公告)日：2011-03-15

申请号：US12438576

申请日：2007-08-09

申请人： Masayuki Mizuno ,  Toru Nakura ,  Koichi Nose

发明人： Masayuki Mizuno ,  Toru Nakura ,  Koichi Nose

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31726 ,  G01R31/31937

摘要： Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs.

摘要翻译： 公开了一种半导体集成电路，包括：第一存储电路和第二存储电路，其在时钟线的逻辑电平改变时分别存储对延迟电路的输入的逻辑电平和延迟电路的输出;以及确定电路 确定第一存储电路和第二存储电路的结果是否一致。 即使构成半导体集成电路的晶体管或布线由于长期变化等而劣化，也可以在异常或异常之前预测由劣化引起的运算电路之一的异常或故障的可能性 发生故障

公开(公告)号：US07893742B2

公开(公告)日：2011-02-22

申请号：US12514115

申请日：2007-10-26

申请人： Atsufumi Shibayama ,  Koichi Nose ,  Masayuki Mizuno

发明人： Atsufumi Shibayama ,  Koichi Nose ,  Masayuki Mizuno

IPC分类号： H03L7/00

CPC分类号： G06F1/10 ,  H03K23/507 ,  H03L7/0814 ,  H03L7/16

摘要： A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit.

摘要翻译： 分频比由N / M（M和N是正整数，满足M> N）调节的时钟信号分频电路包括：可变延迟电路，其基于对输入时钟的控制值给出预定的延迟量 信号CKI输出输出时钟信号CKO; 以及可变延迟控制电路，当相加结果为N以上时，累积地将通过从输入时钟信号CKI的每个周期从M中减去N而获得的值执行从相加结果中减去N的计算，以获得计算结果K ，并且将对应于输入时钟信号CKI的一个周期的可变延迟电路中的最大延迟量计算为与最大延迟量的K / N的延迟量相对应的控制值，以将控制值赋予该变量 延时电路。

公开(公告)号：US07872524B2

公开(公告)日：2011-01-18

申请号：US12439971

申请日：2007-09-13

申请人： Haruya Ishizaki ,  Masayuki Mizuno

发明人： Haruya Ishizaki ,  Masayuki Mizuno

IPC分类号： H03F1/36

CPC分类号： H03F1/22 ,  H03F3/189 ,  H03H7/24 ,  H03H11/245

摘要： [Problems] to provide a CMOS low-noise amplification circuit which can reduce a chip area and design time, and which is easy to be digital-controlled from outside. [Means For Solving the Problems] The amplification circuit includes; an amplification stage (12) which amplifies an input signal up to an intended value; a sample and hold circuit (13) which samples the output signal from the amplification stage (12) by sampling the output signal with a sampling frequency which is at least twice the frequency band of the output signal to convert the output signal to a discrete time signal; a moving average calculation unit (15) which selects and outputs a particular frequency from the discrete time signal outputted from the sample and hold circuit (13) by a moving average operation; and a smoothing filter (17) which smoothes the output signal from the moving average calculation unit (15) and feed it back to the input of the amplification stage (12).

摘要翻译： [问题]提供可以减少芯片面积和设计时间的CMOS低噪声放大电路，并且易于从外部数字控制。 解决问题的手段放大电路包括： 放大级（12），其将输入信号放大到预期值; 采样和保持电路（13），其通过以至少是输出信号的频带的两倍的采样频率对输出信号进行采样来对来自放大级（12）的输出信号进行采样，以将输出信号转换为离散时间 信号; 移动平均计算单元（15），其通过移动平均操作从采样和保持电路（13）输出的离散时间信号中选择并输出特定频率; 以及平滑滤波器（17），其平滑来自移动平均计算单元（15）的输出信号并将其馈送回到放大级（12）的输入端。