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    Techniques for determining parameter variability for interconnects in the presence of manufacturing uncertainty
    1.
    发明申请
    Techniques for determining parameter variability for interconnects in the presence of manufacturing uncertainty 失效

    公开(公告)号：US20060161412A1

    公开(公告)日：2006-07-20

    申请号：US11037531

    申请日：2005-01-18

    申请人： Matthew Angyal ,  Alina Deutsch ,  Ibrahim Elfadel ,  Zhichao Zhang

    发明人： Matthew Angyal ,  Alina Deutsch ,  Ibrahim Elfadel ,  Zhichao Zhang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Techniques are disclosed for determination of parameter variability for one or more given interconnects of a plurality of interconnects in a simulated semiconductor circuit. The simulated semiconductor circuit is defined at least in part by a plurality of input parameters. From a distribution of first values of a given input parameter, a plurality of the first values are determined to use when calculating a corresponding plurality of second values for each of one or more output parameters. By using at least the determined plurality of first values for the given input parameter and selected values for other input parameters in the plurality of input parameters, the corresponding plurality of second values are calculated for each of the one or more output parameters. The one or more output parameters correspond to the one or more given interconnects. Each of the second values corresponds to one of the determined plurality of first values.

    Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures
    2.
    发明申请
    Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures 失效
    用于对片上互连结构进行建模和分析的计算机辅助设计方法和装置

    公开(公告)号：US20050086615A1

    公开(公告)日：2005-04-21

    申请号：US10690238

    申请日：2003-10-21

    申请人： Minakshisundaran Anand ,  Matthew Angyal ,  Alina Deutsch ,  Ibrahim Elfadel ,  Gerard Kopcsay ,  Barry Rubin ,  Howard Smith

    发明人： Minakshisundaran Anand ,  Matthew Angyal ,  Alina Deutsch ,  Ibrahim Elfadel ,  Gerard Kopcsay ,  Barry Rubin ,  Howard Smith

    IPC分类号： G06F9/455 ,  G06F17/50 ,  G06F19/00 ,  G06G7/62

    CPC分类号： G06F17/5036

    摘要： A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.

    摘要翻译： 计算机辅助设计（CAD）系统。 模板生成引擎从互连配置文件生成模板。 场解算器从模板生成高频无源元件关系。 电路构建器从器件技术模型和高频无源元件关系生成电路描述文件。 可以为大范围的灵敏度分析生成参数化电路描述模型。 模拟器模拟来自电路描述文件的传输线模型的电路响应。 互连配置文件可以由接收来自设计者的过程描述数据的几何和材料定义模块生成。

    Techniques for determining parameter variability for interconnects in the presence of manufacturing uncertainty
    3.
    发明授权
    Techniques for determining parameter variability for interconnects in the presence of manufacturing uncertainty 失效
    在存在制造不确定性的情况下确定互连的参数变异性的技术

    公开(公告)号：US07480605B2

    公开(公告)日：2009-01-20

    申请号：US11037531

    申请日：2005-01-18

    申请人： Matthew Stephen Angyal ,  Alina Deutsch ,  Ibrahim M. Elfadel ,  Zhichao Zhang

    发明人： Matthew Stephen Angyal ,  Alina Deutsch ,  Ibrahim M. Elfadel ,  Zhichao Zhang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Techniques are disclosed for determination of parameter variability for one or more given interconnects of a plurality of interconnects in a simulated semiconductor circuit. The simulated semiconductor circuit is defined at least in part by a plurality of input parameters. From a distribution of first values of a given input parameter, a plurality of the first values are determined to use when calculating a corresponding plurality of second values for each of one or more output parameters. By using at least the determined plurality of first values for the given input parameter and selected values for other input parameters in the plurality of input parameters, the corresponding plurality of second values are calculated for each of the one or more output parameters. The one or more output parameters correspond to the one or more given interconnects. Each of the second values corresponds to one of the determined plurality of first values.

    摘要翻译： 公开了用于确定模拟半导体电路中的多个互连的一个或多个给定互连件的参数变化性的技术。 模拟半导体电路至少部分地由多个输入参数定义。 根据给定输入参数的第一值的分布，当为一个或多个输出参数中的每一个计算相应的多个第二值时，确定多个第一值。 通过对于给定的输入参数至少使用所确定的多个第一值和对于多个输入参数中的其他输入参数的选择值，对于一个或多个输出参数中的每一个计算相应的多个第二值。 一个或多个输出参数对应于一个或多个给定互连。 每个第二值对应于所确定的多个第一值中的一个。

    Method, Computer Program and System Providing for Semiconductor Processes Optimization
    4.
    发明申请
    Method, Computer Program and System Providing for Semiconductor Processes Optimization 审中-公开
    方法，提供半导体工艺优化的计算机程序和系统

    公开(公告)号：US20090031260A1

    公开(公告)日：2009-01-29

    申请号：US11782747

    申请日：2007-07-25

    申请人： Matthew Angyal ,  Alina Deutsch ,  Ibrahim M. Elfadel ,  Raminderpal Singh ,  Theodorus E. Standaert ,  Wayne H. Woods

    发明人： Matthew Angyal ,  Alina Deutsch ,  Ibrahim M. Elfadel ,  Raminderpal Singh ,  Theodorus E. Standaert ,  Wayne H. Woods

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/10

    摘要： A method, computer program and system for the optimization of semiconductor process parameters given a pre-specified set of targets and constraints on electrical performance metrics are disclosed. Semiconductor process engineers who are not expert in the art of electrical analysis or mathematical optimization can readily use the method of this invention in optimizing semiconductor process parameters. Accommodates the differences in design styles, metal layer routing, and electrical metrics using priority schedules that are easy to input and understand. Enables the exploration of the process parameter space using primitive process tolerances and accurate electrical information provided by field solvers and circuit analysis programs.

    摘要翻译： 公开了一种用于优化半导体工艺参数的方法，计算机程序和系统，给出了预定指定的一组目标和对电性能度量的约束。 不是电气分析或数学优化领域的专家的半导体工艺工程师可以容易地使用本发明的方法优化半导体工艺参数。 使用易于输入和理解的优先级调度，适应设计风格，金属层布线和电气指标的差异。 使用原始过程公差和现场求解器和电路分析程序提供的准确电气信息来探索过程参数空间。

    X-Y grid tree clock distribution network with tunable tree and grid networks
    5.
    发明授权
    X-Y grid tree clock distribution network with tunable tree and grid networks 失效
    具有可调树和网格网络的X-Y网格树时钟分配网络

    公开(公告)号：US06311313B1

    公开(公告)日：2001-10-30

    申请号：US09222141

    申请日：1998-12-29

    申请人： Peter J. Camporese ,  Alina Deutsch ,  Timothy Gerard McNamara ,  Phillip John Restle ,  David Allan Webber

    发明人： Peter J. Camporese ,  Alina Deutsch ,  Timothy Gerard McNamara ,  Phillip John Restle ,  David Allan Webber

    IPC分类号： G06F945

    CPC分类号： G06F1/10

    摘要： An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid. Electrical simulation models are created for network components and clustered grid loads are substituted with smoothed clustered grid loads. A set of NSECTOR electrical net lists are next created by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors. Each NSECTOR electrical net list is then tuned, wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of each NSECTOR electrical net list.

    摘要翻译： 一个用于在VLSI芯片上分配时钟信号的X-Y网格树时钟分配网络。 可调式接线树网络与X-Y网格结合，垂直和水平连接所有树端点。 在X-Y网格的树端点的连接点不需要驱动程序。 最后的X-Y网格将时钟信号分配到每个需要的地方，并减少局部区域的偏差。 调谐方法允许缓冲时钟信号，同时最小化标称时钟偏移和时钟不确定度。 调谐树网络即使在时钟负载密度和非理想缓冲器放置的变化下也提供低偏移，同时最小化所需的缓冲器数量。 调谐方法首先表示作为集群电网负载的一个或多个时钟引脚负载和布线布线的总电容。 接下来，聚类网格负载的平滑近似于X-Y网格的效果。 为网络组件创建电气仿真模型，并且使用平滑的集群网格负载代替集群网格负载。 接下来通过提取具有相关联的X-Y网格线的网络列表来创建一组NSECTOR电网列表，以将每个扇区网络列表与其相邻扇区隔离。 然后调整每个NSECTOR电网列表，其中平滑的集群网格负载表示每个NSECTOR电网列表的相邻扇区的影响的近似值。

    Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation
    7.
    发明授权
    Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation 失效
    针对频率相关串扰模拟的三维互连结构建模的高效方法

    公开(公告)号：US06418401B1

    公开(公告)日：2002-07-09

    申请号：US09248667

    申请日：1999-02-11

    申请人： Allan H. Dansky ,  Alina Deutsch ,  Gerard V. Kopcsay ,  Phillip J. Restle ,  Howard H. Smith

    发明人： Allan H. Dansky ,  Alina Deutsch ,  Gerard V. Kopcsay ,  Phillip J. Restle ,  Howard H. Smith

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failures—due to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on >10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.

    摘要翻译： 一种减少计算时间并提高设计高性能微处理器芯片的生产率的方法，这些微处理器芯片由于串扰噪声而无故障。 该技术允许非常快速地计算在有损片上互连上精确串扰预测所需的频率相关电路参数表。 这些参数表是在典型微处理器芯片上对> 10K关键网进行串扰检查的CAD工具的基础。 快速表生成允许快速结合设计或处理更改并转换到更先进的技术。

    Electronic structures having a joining geometry providing reduced capacitive loading
    8.
    发明授权
    Electronic structures having a joining geometry providing reduced capacitive loading 失效
    具有提供降低的电容负载的接合几何形状的电子结构

    公开(公告)号：US5471090A

    公开(公告)日：1995-11-28

    申请号：US28023

    申请日：1993-03-08

    申请人： Alina Deutsch ,  David A. Lewis ,  Chandrasekhar Narayan ,  Anthony L. Plachy

    发明人： Alina Deutsch ,  David A. Lewis ,  Chandrasekhar Narayan ,  Anthony L. Plachy

    IPC分类号： H01L23/12 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01L23/48 ,  H01L29/44

    CPC分类号： H01L23/5385 ,  H05K1/0216 ,  H05K1/111 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0289 ,  H05K2201/0373 ,  H05K2201/0792 ,  H05K2201/0939 ,  H05K2201/09427 ,  H05K2201/10719 ,  H05K2203/061 ,  H05K3/4614 ,  Y02P70/611

    摘要： Electrical interconnection structures are described. The electrical interconnection structures are formed by electrically interconnecting in a stack a plurality of discrete substrates. By using a plurality of discrete substrates, a multilayer dielectric/electrical conductor structure can be fabricated from individual discrete substrates each of which can be tested prior to forming a composite stack so that defects in each discrete substrate can be eliminated before inclusion into the stack. Electrical interconnection between adjacent substrate is provided by an array of contact locations on each surface of the adjacent substrates. Corresponding contacts on adjacent substrates are adapted for mutual electrical engagement. Adjacent contact locations can be thermocompression bonded. To reduce the parasitic capacitance and coupled noise between the contact pads and the electrical conductors within the interior of each discrete substrate, the contact pads on each substrate have elongated shape. The elongated contact pads or lattice pads on adjacent substrates are nonparallel and preferably orthogonal so that the corresponding pads of adjacent substrates electrically interconnect an intersecting area which varies in location along the elongated contact pads as the placement of the adjacent substrates varies in the manufacture.

    摘要翻译： 描述电互连结构。 电互连结构通过在堆叠中电互连而形成，多个分立的衬底。 通过使用多个分立的衬底，多层电介质/电导体结构可以由单独的离散衬底制成，每个离散衬底可以在形成复合堆叠之前进行测试，以便在包含在堆叠中之前可以消除每个离散衬底中的缺陷。 相邻基板之间的电气互连通过相邻基板的每个表面上的接触位置阵列来提供。 相邻基板上的相应触点适于相互电接合。 相邻的接触位置可以热压粘合。 为了减小接触焊盘和每个离散衬底内部的电导体之间的寄生电容和耦合噪声，每个衬底上的接触焊盘具有细长形状。 相邻基板上的细长接触焊盘或网格焊盘是不平行的并且优选地是正交的，使得相邻衬底的相应焊盘在制造中随着相邻衬底的布置变化而沿着细长的接触焊盘将位置变化的相交区域电连接。

    Improved bubble domain storage array
    9.
    发明授权
    Improved bubble domain storage array 失效
    改进的气泡域存储阵列

    公开(公告)号：US4221000A

    公开(公告)日：1980-09-02

    申请号：US902657

    申请日：1978-05-04

    申请人： Alina Deutsch ,  Mark H. Kryder ,  Walter Nystrom

    发明人： Alina Deutsch ,  Mark H. Kryder ,  Walter Nystrom

    IPC分类号： G11C11/14 ,  G11C19/08 ,  G11C19/28

    CPC分类号： G11C19/0875 ,  G11C19/0866 ,  G11C19/287 ,  Y10S707/99937

    摘要： A magnetic bubble domain storage system comprising an array of rows and columns of logical chips are organized into logical half-chips with even numbered bits in one half-chip and odd numbered bits in the other half-chip. Alternating rows of half-chips are used for storing even numbered bits and odd numbered bits, respectively. Each half-chip has its own bubble domain generator, but a common generator current line serves all generators for a row of even half-chips and all generators for a row of odd half-chips. Thus, information is written into even half-chips and odd half-chips at the same time by pulsing the generator current line common to a row of even half-chips and a row of odd half-chips. Each half-chip has a sensing element and all the sensing elements corresponding to a row of half-chips are connected in series. The series connection of sensors in any row forms one leg of a bridge circuit, and another leg of the bridge circuit is another series connection of sensors in another row of the storage array. One of these legs corresponds to sensors from a row of even half-chips while the other leg corresponds to sensors from a row of odd half-chips. The other two legs of the bridge circuit are comprised of dummy resistors. Even though two rows of sensors are connected to the same bridge circuit, even numbered bits and odd numbered bits will be read at alternating times.

    摘要翻译： 包括逻辑芯片的行和列的阵列的磁性气泡域存储系统被组织成在另一个半芯片中的一个半芯片和奇数位中具有偶数位的逻辑半芯片。 半芯片的交替行分别用于存储偶数位和奇数位。 每个半芯片都有自己的气泡域发生器，但是通常的发电机电流线为所有发生器提供了一行甚至半芯片，并且所有发生器都用于一排奇数半芯片。 因此，通过脉冲发生器电流线将偶数半芯片和奇数半芯片同时写入偶数半芯片行和奇数半芯片行，将信息写入偶数半芯片和奇数半芯片。 每个半芯片具有感测元件，并且对应于一行半芯片的所有感测元件串联连接。 任何行中的传感器的串联连接形成桥接电路的一条支路，桥接电路的另一条支路是存储阵列的另一行中的传感器的另一串联连接。 这些腿中的一个对应于来自一排偶数半芯片的传感器，而另一条腿对应于来自一排奇数半芯片的传感器。 桥接电路的另外两条支路由虚拟电阻组成。 即使两行传感器连接到相同的桥接电路，偶数位和奇数位将在交替时间读取。