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    Method for manufacturing a semiconductor component that inhibits formation of wormholes
    2.
    发明授权
    Method for manufacturing a semiconductor component that inhibits formation of wormholes 有权
    制造抑制虫洞形成的半导体部件的方法

    公开(公告)号：US07217660B1

    公开(公告)日：2007-05-15

    申请号：US11109964

    申请日：2005-04-19

    申请人： Connie Pin-Chin Wang ,  Paul R. Besser ,  Jinsong Yin ,  Hieu T. Pham ,  Minh Van Ngo

    发明人： Connie Pin-Chin Wang ,  Paul R. Besser ,  Jinsong Yin ,  Hieu T. Pham ,  Minh Van Ngo

    IPC分类号： H01L21/22

    CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L29/6659

    摘要： A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.

    摘要翻译： 一种制造半导体元件的方法，该半导体元件抑制在半导体衬底中形成虫洞。 在设置在半导体衬底上的电介质层中形成接触开口。 接触开口露出半导体衬底的一部分。 在半导体衬底的暴露部分上并沿着接触开口的侧壁形成氧化物牺牲层。 硅烷与六氟化钨反应形成氢氟酸蒸汽和钨。 氢氟酸蒸气蚀刻掉牺牲氧化物层，并且在半导体衬底的暴露部分上形成薄的钨层。 在形成钨的薄层之后，可以改变反应物以更快地用钨填充接触开口。

    Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode
    4.
    发明授权
    Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
    一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极

    公开(公告)号：US06861350B1

    公开(公告)日：2005-03-01

    申请号：US10464508

    申请日：2003-06-19

    申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

    发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H10L21/4763 ,  H10L21/44

    CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545

    摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.

    摘要翻译： 微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。 实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中 的富硅钽硅氮化物。 在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。 实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

    Engineered metal gate electrode
    5.
    发明授权
    Engineered metal gate electrode 有权
    工程金属栅电极

    公开(公告)号：US07033888B2

    公开(公告)日：2006-04-25

    申请号：US10806117

    申请日：2004-03-23

    申请人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

    发明人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966

    摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

    摘要翻译： 形成具有固有电场的金属栅电极，以改变晶体管的功函数和阈值电压。 实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积一层或多层氮化钽，使氮含量从邻近栅介质层的层的底部向上增加。 其他实施例包括通过掺杂一个或多个金属层并形成金属合金来形成本征电场以控制功函数。 实施例还包括在形成金属栅电极时使用阻挡层。

    Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric
    6.
    发明授权
    Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric 有权
    具有金属栅极和高k钽氧化物或氮氧化钽栅极电介质的半导体器件

    公开(公告)号：US07060571B1

    公开(公告)日：2006-06-13

    申请号：US10777138

    申请日：2004-02-13

    申请人： Minh Van Ngo ,  Christy Woo ,  James Pan ,  Paul R. Besser ,  Jinsong Yin

    发明人： Minh Van Ngo ,  Christy Woo ,  James Pan ,  Paul R. Besser ,  Jinsong Yin

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28229 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing a thin tantalum film, as by PVD at a thickness of 25 Å to 60 Å lining the opening, and then conducting thermal oxidation, as at a temperature of 100° C. to 500° C., in flowing oxygen or ozone to form a high-k tantalum oxide gate dielectric layer, or in oxygen and N2O or ozone and N2O ammonia to form a high-k tantalum oxynitride gate dielectric. Alternatively, oxidation can be conducted in an oxygen or ozone plasma to form the high-k tantalum oxide layer, or in a plasma containing N2O and oxygen or ozone to form the high-k tantalum oxynitride gate dielectric layer.

    摘要翻译： 微型半导体器件由具有显着降低的碳的替代金属栅极和高k钽氧化物或氮氧化钽栅极电介质制成。 实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积薄的钽膜，如通过PVD覆盖厚度为25埃至60埃的开口，然后在100℃的温度下进行热氧化 在500℃下，在流动的氧气或臭氧中形成高k氧化钽栅极电介质层，或在氧和N 2 O或臭氧和N 2 O 3 > O氨形成高k钽氮氧化物栅极电介质。 或者，可以在氧气或臭氧等离子体中进行氧化以形成高k钽氧化物层，或者在含有N 2 O的氧化物或臭氧的等离子体中进行氧化以形成高k氮氧化钽栅极 电介质层。

    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS
    9.
    发明申请
    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS 审中-公开
    形成电子器件的方法，包括开孔中的沉积层

    公开(公告)号：US20090050471A1

    公开(公告)日：2009-02-26

    申请号：US11844518

    申请日：2007-08-24

    申请人： Robert J. Chiu ,  Connie Pin-Chin Wang ,  Minh Van Ngo ,  Simon S. Chan

    发明人： Robert J. Chiu ,  Connie Pin-Chin Wang ,  Minh Van Ngo ,  Simon S. Chan

    IPC分类号： C23C14/32

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76814 ,  H01L23/485

    摘要： A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layer. In one embodiment, depositing the first layer is performed at a first alternating current (“AC”) power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove the insulating layer using first metal ions, wherein the first layer includes an overhanging portion extending over the bottom of the opening. In a further embodiment, the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion.

    摘要翻译： 形成电子器件的过程可以包括在衬底上沉积第一层并在第一层上沉积第二层。 在一个实施例中，在第一交流（“AC”）功率下执行沉积第一层，并且以不同于第一AC电力的第二AC电源执行沉积第二层。 在另一个实施例中，第一层通过物理气相沉积技术以足以使用第一金属离子去除绝缘层的第一功率形成，其中第一层包括在开口底部延伸的伸出部分。 在另一个实施例中，第二层通过使用第二金属离子的物理气相沉积技术和足以减少突出部分的横向尺寸的第二功率形成。