公开(公告)号：US10079574B2

公开(公告)日：2018-09-18

申请号：US15019409

申请日：2016-02-09

Applicant: MediaTek Inc.

Inventor： Hsing-ting Yu ,  Fei Song ,  I-Chang Wu ,  YuenHui Chee ,  Chiyuan Lu ,  Keng Leong Fong ,  Osama K. A. Shana'a

IPC: H03F3/45 ,  H03F1/02 ,  H03F3/193 ,  H03F3/21

CPC classification number: H03F1/0222 ,  H03F1/0261 ,  H03F1/0266 ,  H03F1/0277 ,  H03F1/0288 ,  H03F1/48 ,  H03F3/193 ,  H03F3/211 ,  H03F3/245 ,  H03F3/45 ,  H03F3/45071 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/72 ,  H03F2200/18 ,  H03F2200/36 ,  H03F2200/435 ,  H03F2200/451 ,  H03F2200/453 ,  H03F2200/465 ,  H03F2200/555 ,  H03F2203/21106 ,  H03F2203/45311 ,  H03F2203/45352 ,  H03F2203/45368 ,  H03F2203/45544 ,  H03F2203/45674 ,  H03F2203/7206

Abstract: Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

公开(公告)号：US20160365859A1

公开(公告)日：2016-12-15

申请号：US14862520

申请日：2015-09-23

Applicant: MEDIATEK INC.

Inventor： Fei Song ,  Osama Shana'a ,  Yuen Hui Chee

IPC: H03K19/0185 ,  H04B1/40

CPC classification number: H03K19/018514 ,  H03F3/195 ,  H03F3/3001 ,  H03F3/3028 ,  H03F3/3033 ,  H03F3/3037 ,  H03F3/45201 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/21 ,  H03F2200/42 ,  H03F2200/451 ,  H03F2200/498 ,  H03F2200/69 ,  H03F2200/75 ,  H03F2203/45136 ,  H03F2203/45168 ,  H03F2203/45224 ,  H03F2203/45258 ,  H03F2203/45301 ,  H03F2203/45496 ,  H03F2203/45544 ,  H03F2203/45596 ,  H03F2203/45656 ,  H03F2203/45674 ,  H04B1/40 ,  H04B2001/0425

Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

Abstract translation: 呈现低输出阻抗的宽带高线性缓冲电路包括第一PFET（PFET1），第二PFET（PFET2），第一NFET（NFET1）和第二NFET（NFET2）。 PFET1和PFET2的源极耦合到VDD。 PFET1的漏极耦合到输出引线。 PFET2作为电流源。 NFET1的漏极耦合到PFET2的漏极和PFET1的栅极。 NFET1的源极耦合到输出引线。 NFET2的源极耦合到地。 NFET2的漏极耦合到NFET1的源极和输出引线。 NFET1的栅极与第一个输入引线交流耦合。 在单端输入示例中，NFET2的栅极是交流耦合NFET1的漏极。 在差分输入示例中，NFET2的栅极被AC耦合到第二输入引线。 在另一个差分输入示例中，PFET2不仅仅是电流源，而是PFET2的栅极与第一个输入引线交流耦合。

公开(公告)号：US09893728B2

公开(公告)日：2018-02-13

申请号：US14862520

申请日：2015-09-23

Applicant: MEDIATEK INC.

Inventor： Fei Song ,  Osama Shana'a ,  Yuen Hui Chee

IPC: H03B1/00 ,  H03K19/0185 ,  H03F3/195 ,  H03F3/45 ,  H03F3/50 ,  H04B1/40 ,  H03F3/30 ,  H04B1/04

CPC classification number: H03K19/018514 ,  H03F3/195 ,  H03F3/3001 ,  H03F3/3028 ,  H03F3/3033 ,  H03F3/3037 ,  H03F3/45201 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/21 ,  H03F2200/42 ,  H03F2200/451 ,  H03F2200/498 ,  H03F2200/69 ,  H03F2200/75 ,  H03F2203/45136 ,  H03F2203/45168 ,  H03F2203/45224 ,  H03F2203/45258 ,  H03F2203/45301 ,  H03F2203/45496 ,  H03F2203/45544 ,  H03F2203/45596 ,  H03F2203/45656 ,  H03F2203/45674 ,  H04B1/40 ,  H04B2001/0425

Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

公开(公告)号：US20170230006A1

公开(公告)日：2017-08-10

申请号：US15019409

申请日：2016-02-09

Applicant: MediaTek Inc.

Inventor： Hsing-ting Yu ,  Fei Song ,  I-Chang Wu ,  YuenHui Chee ,  Chiyuan Lu ,  Keng Leong Fong ,  Osama K.A. Shana'a

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/193

CPC classification number: H03F1/0222 ,  H03F1/0261 ,  H03F1/0266 ,  H03F1/0277 ,  H03F1/0288 ,  H03F1/48 ,  H03F3/193 ,  H03F3/211 ,  H03F3/245 ,  H03F3/45 ,  H03F3/45071 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/72 ,  H03F2200/18 ,  H03F2200/36 ,  H03F2200/435 ,  H03F2200/451 ,  H03F2200/453 ,  H03F2200/465 ,  H03F2200/555 ,  H03F2203/21106 ,  H03F2203/45311 ,  H03F2203/45352 ,  H03F2203/45368 ,  H03F2203/45544 ,  H03F2203/45674 ,  H03F2203/7206

Abstract: Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

公开(公告)号：US10079702B2

公开(公告)日：2018-09-18

申请号：US14972038

申请日：2015-12-16

Applicant: MediaTek Inc.

Inventor： YuenHui Chee ,  Fei Song ,  James Wang ,  Toru Matsuura ,  Osama K. A. Shana'a ,  Chiyuan Lu

IPC: H04L27/00 ,  H03F3/21 ,  H03F1/02 ,  H03F3/19 ,  H04L25/08 ,  H04B1/40 ,  H03F3/24 ,  H04L27/36 ,  H04B1/04 ,  H03F1/32 ,  H03F3/189 ,  H03F3/20

CPC classification number: H04L27/0002 ,  H03F1/0205 ,  H03F1/3241 ,  H03F1/3247 ,  H03F3/189 ,  H03F3/19 ,  H03F3/20 ,  H03F3/245 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2201/3236 ,  H04B1/0475 ,  H04B1/40 ,  H04B2001/0425 ,  H04L25/08 ,  H04L27/36 ,  H04L27/368

Abstract: Examples of front-end modules, apparatuses and methods for coupling compensation in a closed-loop digital pre-distortion (DPD) system are described. The closed-loop DPD circuit may include a PA and a loopback path. The PA may receive a PA input signal and amplify the PA input signal to provide a PA output signal proportional to a product of the PA input signal and a gain of the PA. The loopback path may receive the PA output signal to output a loopback signal. A forward coupling and a backward coupling may exist between the PA input signal and an output of the loopback path. The output of the loopback path may be proportional to a product of the PA output signal and a gain of the loopback path. The loopback path may include a coupling cancellation mechanism configured to cancel couplings between the PA input signal and the loopback signal.

公开(公告)号：US20160105299A1

公开(公告)日：2016-04-14

申请号：US14972038

申请日：2015-12-16

Applicant: MediaTek Inc.

Inventor： YuenHui Chee ,  Fei Song ,  James Wang ,  Toru Matsuura ,  Osama K.A. Shana'a ,  Chiyuan Lu

IPC: H04L27/00 ,  H03F3/21 ,  H03F1/02 ,  H03F3/19 ,  H04L25/08 ,  H04B1/40

CPC classification number: H04L27/0002 ,  H03F1/0205 ,  H03F1/3241 ,  H03F1/3247 ,  H03F3/189 ,  H03F3/19 ,  H03F3/20 ,  H03F3/245 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2201/3236 ,  H04B1/0475 ,  H04B1/40 ,  H04B2001/0425 ,  H04L25/08 ,  H04L27/36 ,  H04L27/368

Abstract: Examples of front-end modules, apparatuses and methods for coupling compensation in a closed-loop digital pre-distortion (DPD) system are described. The closed-loop DPD circuit may include a PA and a loopback path. The PA may receive a PA input signal and amplify the PA input signal to provide a PA output signal proportional to a product of the PA input signal and a gain of the PA. The loopback path may receive the PA output signal to output a loopback signal. A forward coupling and a backward coupling may exist between the PA input signal and an output of the loopback path. The output of the loopback path may be proportional to a product of the PA output signal and a gain of the loopback path. The loopback path may include a coupling cancellation mechanism configured to cancel couplings between the PA input signal and the loopback signal.

Abstract translation: 描述了用于在闭环数字预失真（DPD）系统中耦合补偿的前端模块，装置和方法的示例。 闭环DPD电路可以包括PA和环回路径。 PA可以接收PA输入信号并放大PA输入信号，以提供与PA输入信号的乘积和PA的增益成比例的PA输出信号。 环回路径可以接收PA输出信号以输出环回信号。 在PA输入信号和环回路径的输出之间可能存在正向耦合和反向耦合。 环回路径的输出可能与PA输出信号与环回路径的增益的乘积成比例。 环回路径可以包括被配置为消除PA输入信号和环回信号之间的耦合的耦合消除机构。