利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

62 条记录 (耗时 0.043 秒)

    Flash EEPROM array with negative gate voltage erase operation
    2.
    发明授权
    Flash EEPROM array with negative gate voltage erase operation 失效
    具有负栅极电压擦除操作的闪存EEPROM阵列

    公开(公告)号：US5077691A

    公开(公告)日：1991-12-31

    申请号：US426332

    申请日：1989-10-23

    申请人： Sameer S. Haddad ,  Chi Chang ,  Antonio Matalvo ,  Michael A. Van Buskirk

    发明人： Sameer S. Haddad ,  Chi Chang ,  Antonio Matalvo ,  Michael A. Van Buskirk

    IPC分类号： G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  G11C29/04 ,  G11C29/50 ,  H01L27/115 ,  H02M3/07

    CPC分类号： G11C29/808 ,  G11C16/16 ,  G11C16/30 ,  G11C29/04 ,  G11C29/50 ,  G11C29/82 ,  H01L27/115 ,  H02M3/073 ,  G11C16/04 ,  G11C2029/5006

    摘要： A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed between the source region of the cell and the bulk substrate, the generation of hot holes is inhibited and improved performance may be obtained. The source region is preferably single diffused rather than double-diffused so that the cell can occupy a minimum area for a given design rule. The low positive voltage applied to the source is preferably less than or equal to the voltage, V.sub.CC presented at a +5V chip power supply pin. This makes it possible for the +5V pin to directly supply source current during erasure.

    摘要翻译： 通过将零参考电压施加到电池的体基板，对于电池的控制栅极的相对高的负电压和到电池的源极区域的相对低的正电压来擦除快闪EEPROM单元阵列。 由于在电池的源极区域和体基板之间产生相对低的反向电压，所以抑制了热孔的产生并且可以获得改进的性能。 源区优选地是单扩散的而不是双扩散的，使得对于给定的设计规则，单元可以占据最小面积。 施加到源极的低正电压优选小于或等于在+ 5V芯片电源引脚处呈现的VCC电压。 这使得+ 5V引脚可以在擦除期间直接提供电源电流。

    Flash memory array with dual function control lines and asymmetrical source and drain junctions
    3.
    发明授权
    Flash memory array with dual function control lines and asymmetrical source and drain junctions 失效
    具有双功能控制线和不对称源极和漏极结的闪存阵列

    公开(公告)号：US06492675B1

    公开(公告)日：2002-12-10

    申请号：US09008162

    申请日：1998-01-16

    申请人： Michael A. Van Buskirk ,  Chi Chang

    发明人： Michael A. Van Buskirk ,  Chi Chang

    IPC分类号： H01L2972

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.

    摘要翻译： 通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。 在一组源极/漏极区域中的每一个中形成不对称的第一和第二结，并且施加化学蚀刻以将场氧化物岛形成氧化物间隔物，其将双功能控制线对准到第一和第二结。 所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

    Flash memory array with dual function control lines and asymmetrical source and drain junctions
    4.
    发明授权
    Flash memory array with dual function control lines and asymmetrical source and drain junctions 失效
    具有双功能控制线和不对称源极和漏极结的闪存阵列

    公开(公告)号：US06744668B1

    公开(公告)日：2004-06-01

    申请号：US10233906

    申请日：2002-09-03

    申请人： Michael A. Van Buskirk ,  Chi Chang

    发明人： Michael A. Van Buskirk ,  Chi Chang

    IPC分类号： G11C1604

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.

    摘要翻译： 通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。 不对称的第一和第二结形成在一组源极/漏极区域中的每一个中，并且施加化学蚀刻以将场氧化物岛形成为将双功能控制线对准到第一和第二结的氧化物间隔物。 所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

    Process for fabricating a flash memory with dual function control lines
    5.
    发明授权
    Process for fabricating a flash memory with dual function control lines 失效
    具有双功能控制线的闪存的制造工艺

    公开(公告)号：US6001689A

    公开(公告)日：1999-12-14

    申请号：US8415

    申请日：1998-01-16

    申请人： Michael A. Van Buskirk ,  Chi Chang

    发明人： Michael A. Van Buskirk ,  Chi Chang

    IPC分类号： H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.

    摘要翻译： 通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。 在一组源极/漏极区域中的每一个中形成不对称的第一和第二结，并且施加化学蚀刻以将场氧化物岛形成氧化物间隔物，其将双功能控制线对准到第一和第二结。 所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

    Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS
    6.
    发明授权
    Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS 失效
    消除5伏隧道氧化物中循环诱导电子捕获的方法，只有闪存EEPROMS

    公开(公告)号：US5485423A

    公开(公告)日：1996-01-16

    申请号：US320368

    申请日：1994-10-11

    申请人： Yuan Tang ,  Chi Chang ,  Michael A. Van Buskirk ,  Chung K. Chang

    发明人： Yuan Tang ,  Chi Chang ,  Michael A. Van Buskirk ,  Chung K. Chang

    IPC分类号： G11C16/14 ,  G11C13/00

    CPC分类号： G11C16/14

    摘要： There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.

    摘要翻译： 提供了一种用于消除快速EEPROM装置的隧道氧化物中的循环诱导电子捕获的改进方法。 在整个擦除周期期间，相对较低的正脉冲电压被施加到EEPROM器件的源极区域。 同时，在整个擦除周期期间，向EEPROM器件的控制栅极施加负斜坡电压，从而实现从擦除周期开始到擦除周期结束的平均隧道场。

    Resistive Devices and Methods of Operation Thereof
    7.
    发明申请
    Resistive Devices and Methods of Operation Thereof 有权
    电阻器件及其操作方法

    公开(公告)号：US20140003125A1

    公开(公告)日：2014-01-02

    申请号：US13610690

    申请日：2012-09-11

    申请人： Foroozan Sarah Koushan ,  Michael A. Van Buskirk

    发明人： Foroozan Sarah Koushan ,  Michael A. Van Buskirk

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0092 ,  G11C2213/74 ,  G11C2213/79

    摘要： In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.

    摘要翻译： 根据本发明的实施例，一种操作电阻式交换设备的方法包括：在具有第一接入终端的接入设备的第一接入终端和第二接入终端上应用包括脉冲的信号。 第二接入终端耦合到两端电阻式交换设备的第一终端。 电阻式开关装置具有第一端子和第二端子。 电阻式开关装置具有第一状态和第二状态。 脉冲包括在第一时间段内从第一电压到第二电压的第一斜坡，在第二时间段内从第二电压到第三电压的第二斜坡，以及从第三电压到第四电压的第三斜坡 第三个时期。 第二斜坡和第三斜坡与第一坡道具有相反的斜坡。 第一时间段和第二时间段的总和小于第三时间段。

    Techniques for providing a semiconductor memory device
    8.
    发明授权
    Techniques for providing a semiconductor memory device 有权
    提供半导体存储器件的技术

    公开(公告)号：US08547738B2

    公开(公告)日：2013-10-01

    申请号：US13047097

    申请日：2011-03-14

    申请人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

    发明人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

    IPC分类号： G11C11/34

    CPC分类号： H01L27/10802 ,  G11C7/00 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/1095 ,  H01L29/7841

    摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.

    摘要翻译： 公开了一种用于提供半导体存储器件的技术。 在一个特定示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储器单元的半导体存储器件。 每个存储单元包括电容耦合到至少一个字线并且设置在第一区域和第二区域之间的第一区域，第二区域和体区域。 每个存储单元还包括第三区域，其中第三区域可以掺杂不同于第一区域，第二区域和体区域。

    Techniques for providing a direct injection semiconductor memory device
    9.
    发明授权
    Techniques for providing a direct injection semiconductor memory device 有权
    提供直接注入半导体存储器件的技术

    公开(公告)号：US08315099B2

    公开(公告)日：2012-11-20

    申请号：US12844477

    申请日：2010-07-27

    申请人： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    发明人： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    IPC分类号： G11C16/04

    CPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

    摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.

    摘要翻译： 公开了提供直接注入半导体存储器件的技术。 在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。 多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。 多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。 多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一 其他。

    TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE 有权
    提供直接注入半导体存储器件的技术

    公开(公告)号：US20110019482A1

    公开(公告)日：2011-01-27

    申请号：US12844477

    申请日：2010-07-27

    申请人： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    发明人： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

    IPC分类号： G11C16/04

    CPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

    摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.

    摘要翻译： 公开了提供直接注入半导体存储器件的技术。 在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。 多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。 多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。 多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一 其他。