公开(公告)号：US5335198A

公开(公告)日：1994-08-02

申请号：US57583

申请日：1993-05-06

申请人： Michael A. Van Buskirk ,  Kevin W. Plouse ,  Joseph G. Pawletko ,  Chi Chang ,  Sameer S. Haddad ,  Ravi P. Gutala

发明人： Michael A. Van Buskirk ,  Kevin W. Plouse ,  Joseph G. Pawletko ,  Chi Chang ,  Sameer S. Haddad ,  Ravi P. Gutala

IPC分类号： G11C16/28 ,  G11C16/34 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50

CPC分类号： G11C29/82 ,  G11C16/28 ,  G11C16/3404 ,  G11C16/3409 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50 ,  G11C29/88 ,  G11C16/04 ,  G11C2029/5006

摘要： An over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells during programming operations so as to render high endurance. Sensing circuitry (23) is used to detect column leakage current indicative of an over-erased bit. If an over-erased bit is determined, a pulse counter (25) is activated so as to apply programming pulses to the control gate of the selected memory cell so as to program back the negative threshold voltage of the over-erased bit to a positive voltage.

摘要翻译： 提供了一种过擦除位校正结构，用于在编程操作期间对闪存EEPROM存储器单元阵列中的擦除过的存储器单元进行校正操作，以使其具有高耐久性。 感测电路（23）用于检测指示过擦除位的列泄漏电流。 如果确定了过擦除位，则激活脉冲计数器（25），以便将编程脉冲施加到所选存储单元的控制栅极，以便将过擦除位的负阈值电压反馈到正 电压。

公开(公告)号：US5077691A

公开(公告)日：1991-12-31

申请号：US426332

申请日：1989-10-23

申请人： Sameer S. Haddad ,  Chi Chang ,  Antonio Matalvo ,  Michael A. Van Buskirk

发明人： Sameer S. Haddad ,  Chi Chang ,  Antonio Matalvo ,  Michael A. Van Buskirk

IPC分类号： G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  G11C29/04 ,  G11C29/50 ,  H01L27/115 ,  H02M3/07

CPC分类号： G11C29/808 ,  G11C16/16 ,  G11C16/30 ,  G11C29/04 ,  G11C29/50 ,  G11C29/82 ,  H01L27/115 ,  H02M3/073 ,  G11C16/04 ,  G11C2029/5006

摘要： A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed between the source region of the cell and the bulk substrate, the generation of hot holes is inhibited and improved performance may be obtained. The source region is preferably single diffused rather than double-diffused so that the cell can occupy a minimum area for a given design rule. The low positive voltage applied to the source is preferably less than or equal to the voltage, V.sub.CC presented at a +5V chip power supply pin. This makes it possible for the +5V pin to directly supply source current during erasure.

摘要翻译： 通过将零参考电压施加到电池的体基板，对于电池的控制栅极的相对高的负电压和到电池的源极区域的相对低的正电压来擦除快闪EEPROM单元阵列。 由于在电池的源极区域和体基板之间产生相对低的反向电压，所以抑制了热孔的产生并且可以获得改进的性能。 源区优选地是单扩散的而不是双扩散的，使得对于给定的设计规则，单元可以占据最小面积。 施加到源极的低正电压优选小于或等于在+ 5V芯片电源引脚处呈现的VCC电压。 这使得+ 5V引脚可以在擦除期间直接提供电源电流。

公开(公告)号：US5875130A

公开(公告)日：1999-02-23

申请号：US085705

申请日：1998-05-27

申请人： Sameer S. Haddad ,  Wing H. Leung ,  John Chen ,  Ravi S. Sunkavalli ,  Ravi P. Gutala ,  Jonathan S. Su ,  Vei-Han Chan ,  Colin S. Bill

发明人： Sameer S. Haddad ,  Wing H. Leung ,  John Chen ,  Ravi S. Sunkavalli ,  Ravi P. Gutala ,  Jonathan S. Su ,  Vei-Han Chan ,  Colin S. Bill

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C13/00

CPC分类号： G11C16/3409 ,  G11C16/10 ,  G11C16/3404

摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse. The bias voltage is preferably applied during both the overerase correction and programming pulses, reducing the power requirements and reducing the background leakage of the cells to a level at which program, read and overerase correction operations can be operatively performed.

摘要翻译： 闪存电可擦除可编程只读存储器（EEPROM）包括半导体衬底和多个场效应晶体管存储单元，每个具有形成在衬底上的源极，漏极，浮置栅极和控制栅极。 控制器控制电源以将操作脉冲施加到单元的漏极，并且在施加操作脉冲时将源施加到单元的衬底偏置电压，所述偏置电压具有被选择为减少或基本上消除的值 电池中的漏电流。 操作脉冲可以是过高修正脉冲。 在这种情况下，在过扫描校正脉冲的持续时间内，向控制栅极施加基本上等于偏置电压的电压。 操作脉冲也可以是编程脉冲。 在这种情况下，在编程脉冲的持续时间内，将高于偏置电压的电压施加到所选字线的控制栅极。 偏置电压优选地在过电压过程校正和编程脉冲期间都被施加，从而降低功率需求并将电池的背景泄漏减小到能够可操作地执行程序，读取和过电压校正操作的电平。

公开(公告)号：US6157572A

公开(公告)日：2000-12-05

申请号：US85680

申请日：1998-05-27

申请人： Sameer S. Haddad ,  Wing H. Leung ,  John Chen ,  Ravi S. Sunkavalli ,  Ravi P. Gutala ,  Jonathan S. Su ,  Vei-Han Chen ,  Colin S. Bill

发明人： Sameer S. Haddad ,  Wing H. Leung ,  John Chen ,  Ravi S. Sunkavalli ,  Ravi P. Gutala ,  Jonathan S. Su ,  Vei-Han Chen ,  Colin S. Bill

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/16

摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power supply for generating erase pulses. A controller controls the power supply to apply an erase pulse to all wordlines which are not deselected. Then, an erase verify procedure is applied to the cells in sequence. If all cells connected to a wordline pass the erase verify test, the wordline is deselected such that subsequent erase pulses will not be applied to the wordline and possibly cause the cells to become overerased. In one embodiment of the invention, erase verify is performed on all of the cells after an erase pulse is applied. The erase operation is completed when all cells pass erase verify. In another embodiment, erase verify is applied to each cell in sequence, with erase pulses being applied until each current cell passes erase verify. The wordlines can be deselected individually or in groups. The invention results in a tightening of the threshold voltage distribution of the cells.

摘要翻译： 闪存电可擦除可编程只读存储器（EEPROM）包括多个浮栅晶体管存储单元，连接到单元的多个字线和用于产生擦除脉冲的电源。 控制器控制电源以将擦除脉冲施加到未被取消选择的所有字线。 然后，按顺序对单元应用擦除验证程序。 如果连接到字线的所有单元都通过擦除验证测试，则字线被取消选择，使得后续的擦除脉冲不会被施加到字线并且可能导致单元变得过高。 在本发明的一个实施例中，在施加擦除脉冲之后对所有单元执行擦除验证。 当所有单元通过擦除验证时，擦除操作完成。 在另一实施例中，按顺序对每个单元施加擦除验证，其中施加擦除脉冲，直到每个当前单元通过擦除验证。 字母可以单独或分组取消选择。 本发明导致电池的阈值电压分布的紧缩。

公开(公告)号：US5901090A

公开(公告)日：1999-05-04

申请号：US85552

申请日：1998-05-27

申请人： Sameer S. Haddad ,  Wing H. Leung ,  John Chen ,  Ravi S. Sunkavalli ,  Ravi P. Gutala ,  Jonathan S. Su ,  Colin S. Bill ,  Vei-Han Chen

发明人： Sameer S. Haddad ,  Wing H. Leung ,  John Chen ,  Ravi S. Sunkavalli ,  Ravi P. Gutala ,  Jonathan S. Su ,  Colin S. Bill ,  Vei-Han Chen

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/3409 ,  G11C16/16

摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the power source to apply at least one erase pulse to the cells. Then, at least one overerase correction or "soft programming" pulse is applied to the cells during which the source, drain and control gate voltages of the cells are such that the threshold voltages of overerased cells will be increased, but least erased cells will not be disturbed. The overerase correction pulses thereby tighten the threshold voltage distribution. A source to substrate bias voltage is applied for the duration of the overerase correction pulses which reduces the background leakage of the cells to a level at which the overerase correction operation can be effectively performed, even in applications with low supply voltages.

摘要翻译： 闪存电可擦除可编程只读存储器（EEPROM）包括多个具有源极，漏极，浮动栅极和控制栅极的场效应晶体管存储单元，以及用于向单元提供多个电压的电源。 控制器控制电源向单元施加至少一个擦除脉冲。 然后，将至少一个过度校正或“软编程”脉冲施加到单元，在该单元期间，单元的源极，漏极和控制栅极电压使得过度流过的单元的阈值电压将增加，但是最小擦除的单元将不会 被打扰 过度校正脉冲从而使阈值电压分布紧密。 在过渡期校正脉冲的持续时间内施加衬底偏置电压源，即使在具有低电源电压的应用中，也可以将电池的背景泄漏降低到可以有效执行过电压修正操作的水平。

公开(公告)号：US06808996B1

公开(公告)日：2004-10-26

申请号：US09376659

申请日：1999-08-18

申请人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

发明人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.

摘要翻译： 制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。 然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。 然后将掺杂剂注入漏区。 在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

公开(公告)号：US06252803B1

公开(公告)日：2001-06-26

申请号：US09692881

申请日：2000-10-23

申请人： Richard Fastow ,  Sameer S. Haddad ,  Lee E. Cleveland ,  Chi Chang

发明人： Richard Fastow ,  Sameer S. Haddad ,  Lee E. Cleveland ,  Chi Chang

IPC分类号： G11C1616

CPC分类号： G11C16/16

摘要： A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value. This cycle is repeated until all of those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value are brought above the pre-defined minimum value. The erase method is considered to be finished when there are no memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.

摘要翻译： 提供擦除闪存电可擦除可编程只读存储器（EEPROM）设备的方法，其包括多个存储器单元。 擦除脉冲被施加到多个存储单元。 多个存储器单元被过度验证，并且过高修正脉冲被施加到被过度存储的存储单元附着的位线。 重复此循环，直到所有的单元格都被验证为不被过高。 多个存储器单元被擦除验证，并且如果存在未存储的存储器单元并且存储器单元再次被擦除验证，则另一个擦除脉冲被施加到存储器单元。 重复此循环，直到所有单元格都被验证为不被忽略。 在擦除验证完成之后，多个存储器单元被软件程序验证，并且将软编程脉冲施加到具有低于预定义最小值的阈值电压的多个存储单元中的那些存储单元。 重复该循环，直到具有低于预定义最小值的阈值电压的多个存储器单元中的所有那些存储器单元高于预定义的最小值。 当多个存储单元中没有存储单元的阈值电压低于预先定义的最小值时，擦除方法被认为是完成的。

公开(公告)号：US06455373B1

公开(公告)日：2002-09-24

申请号：US09834419

申请日：2001-04-12

申请人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

发明人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11536

摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).

摘要翻译： 在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入 顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏 选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

公开(公告)号：US06248627B1

公开(公告)日：2001-06-19

申请号：US09376658

申请日：1999-08-18

申请人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

发明人： Tuan D. Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11536

摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.

摘要翻译： 制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。 然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。 然后将掺杂剂注入漏区。 在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

公开(公告)号：US5590076A

公开(公告)日：1996-12-31

申请号：US493138

申请日：1995-06-21

申请人： Sameer S. Haddad ,  Chi Chang ,  David K. Y. Liu

发明人： Sameer S. Haddad ,  Chi Chang ,  David K. Y. Liu

IPC分类号： G11C16/02 ,  G11C16/10 ,  G11C7/00

CPC分类号： G11C16/10

摘要： Disclosed herein is a channel hot-carrier page write including an array of stacked gate flash EEPROM memory cells operating in a very low energy programming mode permitting page writing of 1024 bits within a 20-100 .mu.S programming interval. Internal programming voltage levels are derived from on-chip circuits, such as charge pumps, operated from a single +V.sub.CC source. In a preferred embodiment, a cache memory buffers data transfers between a computer bus and the page oriented storage array. In another embodiment, core doping is increased in the channel and drain regions to enhance hot carrier injection and to lower the programming drain voltage. The stacked floating gate structure is shown to exhibit a high programming efficiency in a range from 10.sup.-6 to 10.sup.-4 at drain voltages below 5.2 VDC. In another embodiment AC components of the programming current are minimized by precharging a common source line at the start of a programming cycle.

摘要翻译： 本文公开了一种通道热载体页面写入，其包括以非常低能量编程模式操作的堆叠栅极快闪EEPROM存储器单元的阵列，允许在20-100μs编程间隔内1024页的页写入。 内部编程电压电平源自片上电路，如电荷泵，由单个+ VCC源运行。 在优选实施例中，高速缓冲存储器缓冲计算机总线和面向页面的存储阵列之间的数据传输。 在另一个实施例中，在沟道和漏极区域中增加了芯掺杂以增强热载流子注入并降低编程漏极电压。 堆叠的浮置栅极结构在低于5.2VDC的漏极电压下表现出在10-6至10-4的范围内的高编程效率。 在另一个实施例中，通过在编程周期开始时对公共源极线进行预充电，使编程电流的AC分量最小化。