公开(公告)号：US5521108A

公开(公告)日：1996-05-28

申请号：US121679

申请日：1993-09-15

申请人： Michael D. Rostoker ,  Ashok Kapoor

发明人： Michael D. Rostoker ,  Ashok Kapoor

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423

CPC分类号： H01L29/66825 ,  H01L21/2807 ,  H01L27/11517 ,  H01L29/42324 ,  Y10S148/059

摘要： A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the roughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed. A further oxide layer may then be formed over the second conductive layer followed by a patterning step to respectively form the floating gate (from the germanium/silicon layer) and the control gate from the second conductive layer.

摘要翻译： 描述了导电构件，其上具有受控粗糙度的表面，其可用于集成电路结构的构造。 在优选实施例中，使用锗和硅的混合物形成导电构件，然后将其氧化，导致在锗/硅导电构件上形成粗糙表面，这是由于锗的氧化速率的差异 和硅。 在氧化导电部件之后，可以去除氧化物层，使锗/硅导电部件上的粗糙表面残留。 当使用具有粗糙表面的导电部件形成诸如EPROM的集成电路结构时，然后在粗糙表面上沉积另外的氧化物层，随后沉积第二层导电材料，例如多晶硅或锗 /硅混合物，从其形成控制栅极。 然后可以在第二导电层上形成另外的氧化物层，接着形成图案化步骤以分别从第二导电层形成浮栅（来自锗/硅层）和控制栅极。

公开(公告)号：US5644152A

公开(公告)日：1997-07-01

申请号：US462653

申请日：1995-06-05

申请人： Michael D. Rostoker ,  Ashok Kapoor

发明人： Michael D. Rostoker ,  Ashok Kapoor

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/161 ,  H01L29/34

CPC分类号： H01L29/66825 ,  H01L21/2807 ,  H01L27/11517 ,  H01L29/42324 ,  Y10S148/059

摘要： A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the toughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed. A further oxide layer may then be formed over the second conductive layer followed by a patterning step to respectively form the floating gate (from the germanium/silicon layer) and the control gate from the second conductive layer.

摘要翻译： 描述了导电构件，其上具有受控粗糙度的表面，其可用于集成电路结构的构造。 在优选实施例中，使用锗和硅的混合物形成导电构件，然后将其氧化，导致在锗/硅导电构件上形成粗糙表面，这是由于锗的氧化速率的差异 和硅。 在氧化导电部件之后，可以去除氧化物层，留下锗/硅导电部件上的增韧表面。 当使用具有粗糙表面的导电部件形成诸如EPROM的集成电路结构时，然后在粗糙表面上沉积另外的氧化物层，随后沉积第二层导电材料，例如多晶硅或锗 /硅混合物，从其形成控制栅极。 然后可以在第二导电层上形成另外的氧化物层，接着形成图案化步骤以分别从第二导电层形成浮栅（来自锗/硅层）和控制栅极。

公开(公告)号：US5982659A

公开(公告)日：1999-11-09

申请号：US779998

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Thomas R. Wik ,  Raymond T. Leung ,  Ashok Kapoor ,  Alex Owens

发明人： V. Swamy Irrinki ,  Thomas R. Wik ,  Raymond T. Leung ,  Ashok Kapoor ,  Alex Owens

IPC分类号： G11C11/56 ,  G11C17/00 ,  G11C17/14

CPC分类号： G11C17/00 ,  G11C11/56 ,  G11C11/5692 ,  G11C7/16

摘要： A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

摘要翻译： 能够在存储器单元中存储多于两个逻辑状态的过程。 在一个实施例中，通孔用于在字读取线和数据读取线之间耦合二极管。 通孔具有在制造时被设置为多个值之一的电阻。 当字读取线被断言时，贯穿通孔的电压降指示存储的逻辑状态。 模数（A / D）转换器耦合到数据读取线，以便感测电压降并确定所表示的状态。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。

公开(公告)号：US5784328A

公开(公告)日：1998-07-21

申请号：US779999

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond Leung ,  Alex Owens ,  Thomas R. Wik

发明人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond Leung ,  Alex Owens ,  Thomas R. Wik

IPC分类号： G11C11/406 ,  G11C11/56 ,  G11C7/00

CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/565 ,  G11C16/3418 ,  G11C16/3431

摘要： A DRAM memory array including a temperature sensor for adjusting a refresh rate depending upon temperature. The DRAM memory array includes a plurality of memory cells, each configured to allow storage and retrieval of more than two discrete memory states. A refresh circuit is coupled to the memory array for periodically refreshing the discrete storage state of each memory cell. The temperature sensor is situated on the same semiconductor die upon which the memory array is fabricated, and generates a signal indicative of the temperature of the semiconductor die. A control circuit receives the signal from the temperature sensor and responsively generates a refresh rate signal which is provided to control the refresh rate of the refresh circuit. In one specific implementation, a ROM look-up table is coupled to the control circuit and includes a plurality of entries which indicate the desired refresh rates for particular temperatures. By controlling the refresh rate dependent upon the temperature of the semiconductor die, proper state retention is ensured within each of the memory cells while allowing performance to be optimized.

摘要翻译： 一种DRAM存储器阵列，包括用于根据温度调节刷新率的温度传感器。 DRAM存储器阵列包括多个存储器单元，每个存储器单元被配置为允许存储和检索多于两个的离散存储器状态。 刷新电路耦合到存储器阵列，用于周期性地刷新每个存储单元的离散存储状态。 温度传感器位于制造存储器阵列的相同的​​半导体管芯上，并且产生表示半导体管芯的温度的信号。 控制电路接收来自温度传感器的信号，并且响应地产生刷新率信号，该信号被提供以控制刷新电路的刷新率。 在一个具体实现中，ROM查找表耦合到控制电路，并且包括指示特定温度的期望刷新率的多个条目。 通过根据半导体管芯的温度控制刷新率，确保每个存储单元内的适当的状态保持，同时允许优化性能。

公开(公告)号：US5771187A

公开(公告)日：1998-06-23

申请号：US779994

申请日：1996-12-23

申请人： Ashok Kapoor

发明人： Ashok Kapoor

IPC分类号： G11C11/56 ,  G11C11/24

CPC分类号： G11C11/565 ,  G11C7/16

摘要： A semiconductor memory device which includes a word line, a bit line and a storage capacitor having first and second ends. A pair of FEATS each having gates coupled to the word line and one side coupled to the bit line. The other side of each FEAT is coupled to a storage capacitor upon which a selected one of four potential levels, corresponding to stored values of zero, one, two, or three, can be stored and thereafter read. One of the FEATS has a thicker gate oxide than the other and thus a higher threshold voltage. Voltage stored on the capacitor is read in two cycles thereby producing in the first cycle a high level pulse, a low level pulse, or no pulse and in the second cycle, a low level pulse or no pulse, depending upon the level of charge stored on the capacitor.

摘要翻译： 一种半导体存储器件，包括字线，位线和具有第一和第二端的存储电容器。 一对FEATS，每一个具有耦合到字线的栅极和耦合到位线的一侧。 每个FEAT的另一侧耦合到存储电容器，在存储电容器上可以存储对应于存储的零，一个，二个或三个值的四个电位电平中的所选择的一个，然后读取。 其中一个FEATS具有比另一个更厚的栅极氧化物，因此具有较高的阈值电压。 存储在电容器上的电压被读取两个周期，从而在第一周期中产生高电平脉冲，低电平脉冲或无脉冲，并且在第二周期中，根据存储的电荷电平产生低电平脉冲或无脉冲 在电容上。

公开(公告)号：US5061986A

公开(公告)日：1991-10-29

申请号：US476149

申请日：1990-02-05

申请人： Madhukar Vora ,  Greg Burton ,  Ashok Kapoor

发明人： Madhukar Vora ,  Greg Burton ,  Ashok Kapoor

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108 ,  H01L27/11

CPC分类号： H01L21/28518 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/10805 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/3011

摘要： There is disclosed herein a bipolar transistor structure having a self aligned extended silicide base contact. The contact extends to the position of a base contact window located outside the perimeter of the isolation island on a contact pad formed over the field oxide. This allows the size of the isolation island to be kept smaller and allows a smaller extrinsic base regions to be formed. The base contact is formed of titanium and titanium silicide where the titanium/silicide boundary is self aligned with the edge of the device isolation island. The silicide is formed by reacting the titanium which completely covers the exposed epitaxial silicon inside the isolation island. An anisotropically etched oxide sidewall spacer insulates the silicide from the sidewall of the silicide-covered, polysilicon emitter contact.

摘要翻译： 本文公开了具有自对准的延伸硅化物基极接触的双极晶体管结构。 接触件延伸到位于场氧化物上形成的接触垫上的位于隔离岛的周边外部的基底接触窗口的位置。 这允许隔离岛的尺寸保持较小并且允许形成更小的非本征基区。 基极接触由钛和硅化钛形成，其中钛/硅化物边界与器件隔离岛的边缘自对准。 硅化物通过使完全覆盖隔离岛内的暴露的外延硅的钛反应而形成。 各向异性蚀刻的氧化物侧壁间隔物将硅化物与硅化物覆盖的多晶硅发射极接触的侧壁绝缘。

公开(公告)号：US20070126478A1

公开(公告)日：2007-06-07

申请号：US11635004

申请日：2006-12-07

申请人： Ashok Kapoor

发明人： Ashok Kapoor

IPC分类号： H03K19/0175

CPC分类号： H03K19/0941 ,  H01L27/098 ,  H01L29/66901 ,  H01L29/808 ,  H03K2217/0018

摘要： A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.

摘要翻译： 提供了一种使用具有小线宽的一对互补结场效应晶体管（CJFET）的逆变器的方法。 该方法包括使所述CJFET反相器的输入电容小于类似线宽的CMOS反相器的相应输入电容。 与所述CMOS反相器相比，CJFET工作在比具有降低的开关功率的正向偏置二极管的电压降低的电源，并且具有至少与相应延迟相当的所述CJFET反相器的传播延迟 的CMOS反相器。

公开(公告)号：US20070069306A1

公开(公告)日：2007-03-29

申请号：US11533332

申请日：2006-09-19

申请人： Ashok Kapoor ,  Robert Strain ,  Reuven Marko

发明人： Ashok Kapoor ,  Robert Strain ,  Reuven Marko

IPC分类号： H01L29/94

CPC分类号： H01L27/0629 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/78 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

摘要： An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

摘要翻译： 公开了一种用于金属氧化物半导体（MOS）晶体管的装置和制造方法。 根据本发明的装置可在低于2V的电压下工作。 这些器件具有区域有效性，具有改进的驱动强度，并且具有减小的漏电流。 使用包括与电容器并联的正向偏置二极管的动态阈值电压控制方案，而不改变现有的MOS技术过程。 该方案控制每个晶体管的阈值电压。 在OFF状态下，晶体管的阈值电压的大小增加，保持晶体管漏电量最小。 在ON状态下，阈值电压的大小减小，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 还示出了与上述结构一起使用阱的反向偏置以进一步减小MOS晶体管中的泄漏。

公开(公告)号：US6005264A

公开(公告)日：1999-12-21

申请号：US396541

申请日：1995-03-01

申请人： Ashok Kapoor

发明人： Ashok Kapoor

IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L27/118 ,  H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/11807 ,  H01L27/0922

摘要： A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of CMOS microelectronic devices formed on the substrate. Each device includes a hexagonal ANY element of a first conductivity type (PMOS or NMOS), and a hexagonal ALL element of a second conductivity type (NMOS or PMOS), the ANY and ALL elements each having a plurality of inputs and an output that are electrically interconnected respectively. The ANY element is basically an OR element, and the ALL element is basically an AND element. However, the power supply connections and the selection of conductivity type (NMOS or PMOS) for the ANY and ALL elements can be varied to provide the device as having a desired NAND, AND, NOR or OR configuration, in which the ANY element acts as a pull-up and the ALL element acts as a pull-down, or vice-versa.

摘要翻译： 微电子集成电路包括半导体衬底和形成在衬底上的多个CMOS微电子器件。 每个器件包括第一导电类型（PMOS或NMOS）的六边形ANY元件和第二导电类型（NMOS或PMOS）的六边形ALL元件，每个ANY和ALL元件都具有多个输入端和输出端 电连接。 ANY元素基本上是一个OR元素，ALL元素基本上是AND元素。 然而，可以改变ANY和ALL元件的电源连接和导电类型（NMOS或PMOS）的选择，以使器件具有所需的NAND，AND，NOR或OR配置，其中ANY元件作为 上拉和ALL元素作为下拉，反之亦然。

公开(公告)号：US5847990A

公开(公告)日：1998-12-08

申请号：US779993

申请日：1996-12-23

申请人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

发明人： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC分类号： G11C11/41 ,  G11C11/56 ,  G11C11/00

CPC分类号： G11C11/5621 ,  G11C11/412 ,  G11C7/16

摘要： A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.

摘要翻译： 一种能够在存储单元中存储三种逻辑状态的存储电路。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。 所公开的存储器电路包括耦合以检测通过存储器单元中的晶体管的电流的模拟 - 数字转换器。 电流由三态触发器的状态决定。 通过使电流被检测为正，负或零，可以用触发器的状态表示多于一个位的信息。