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144 条记录 (耗时 0.044 秒)

    Keypad scanner
    1.
    发明授权
    Keypad scanner 失效
    键盘扫描仪

    公开(公告)号：US5621402A

    公开(公告)日：1997-04-15

    申请号：US95923

    申请日：1993-07-21

    申请人： Michael E. Spak ,  Dale E. Gulick

    发明人： Michael E. Spak ,  Dale E. Gulick

    IPC分类号： G06F3/02 ,  G06F3/023 ,  H03M11/20 ,  H03K17/94

    CPC分类号： H03M11/20

    摘要： A keypad scanner for a keypad having a plurality of keys which may be pressed into a down state includes circuitry for detecting when no or any key is pressed down and thereupon generating a no or any key down signal, circuitry for detecting when more than one key is pressed down and thereupon generating a multiple key down signal, and an interrupt generator coupled to the aforementioned circuitry. The interrupt generator itself includes circuitry for detecting a change in no or any key down signal level, circuitry for detecting a change in multiple key down signal level, and circuitry for generating an interrupt signal when either the circuitry for detecting a change in no or any key down signal level or the circuitry for detecting a change in multiple key down signal level detects a change.

    摘要翻译： 用于具有可以被按压到下降状态的多个键的小键盘的键盘扫描器包括用于检测什么时候没有或任何键被按下并且随后产生无或任何键降低信号的电路，用于检测何时多于一个键 被按下并随后产生多重按键信号，以及耦合到上述电路的中断发生器。 中断发生器本身包括用于检测无或任何按键降低信号电平变化的电路，用于检测多个键下降信号电平变化的电路，以及用于当用于检测否或任何信号的改变的电路时产生中断信号的电路 键下降信号电平或用于检测多重键下降信号电平变化的电路检测到变化。

    Initialization of a computer system including a secure execution mode-capable processor
    4.
    发明授权
    Initialization of a computer system including a secure execution mode-capable processor 有权
    包括安全执行模式处理器的计算机系统的初始化

    公开(公告)号：US07603551B2

    公开(公告)日：2009-10-13

    申请号：US10419121

    申请日：2003-04-18

    申请人： Kevin J. McGrath ,  Geoffrey S. Strongin ,  David S. Christie ,  William A. Hughes ,  Dale E. Gulick

    发明人： Kevin J. McGrath ,  Geoffrey S. Strongin ,  David S. Christie ,  William A. Hughes ,  Dale E. Gulick

    IPC分类号： G06F9/44 ,  H04L29/06

    CPC分类号： G06F9/4403

    摘要： The initialization of a computer system including a secure execution mode-capable processor includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory. The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.

    摘要翻译： 包括具有安全执行模式能力的处理器的计算机系统的初始化包括将安全操作系统代码段加载器存储到对应于系统存储器内的特定地址范围的多个位置。 该方法还包括执行安全初始化指令。 执行安全初始化指令可能导致执行若干操作，包括发送包括特定地址范围的基地址的开始事务。 此外，执行安全指令还可以引起执行另一操作，包括从系统存储器检索安全操作系统代码段加载器，并将安全操作系统代码段加载器发送为多个数据事务。

    Enhanced security and manageability using secure storage in a personal computer system
    5.
    发明授权
    Enhanced security and manageability using secure storage in a personal computer system 有权
    在个人计算机系统中使用安全存储来增强安全性和可管理性

    公开(公告)号：US07216362B1

    公开(公告)日：2007-05-08

    申请号：US09853395

    申请日：2001-05-11

    申请人： Geoffrey S. Strongin ,  Dale E. Gulick

    发明人： Geoffrey S. Strongin ,  Dale E. Gulick

    IPC分类号： G06F12/14 ,  G06F12/00 ,  G06F7/04 ,  G06F13/00

    CPC分类号： G06F12/1441 ,  G06F7/582 ,  G06F12/1458 ,  G06F21/53 ,  G06F21/72

    摘要： A method and system for enhanced security and manageability using secure storage. The system may include a crypto-processor and a memory coupled to receive memory transactions through the crypto-processor. The memory transactions are passed to the memory by the crypto-processor. The system may include a first processor, a second processor coupled to the first processor, and a storage device operably coupled to the first processor through the second processor. The second processor is configured to control access to the storage device. The method includes transmitting a request for a memory transaction for a storage location in the storage device and receiving the request for the memory transaction at the crypto-processor. The method also includes determining if the memory transaction is authorized for the storage location, and passing the request for the memory transaction to the storage device if the memory transaction is authorized for the storage location.

    摘要翻译： 一种使用安全存储来增强安全性和可管理性的方法和系统。 该系统可以包括加密处理器和耦合以通过密码处理器接收存储器事务的存储器。 存储器事务由加密处理器传递到存储器。 该系统可以包括第一处理器，耦合到第一处理器的第二处理器，以及通过第二处理器可操作地耦合到第一处理器的存储设备。 第二处理器被配置为控制对存储设备的访问。 该方法包括向存储设备发送对存储位置的存储器事务的请求，并在密码处理器处接收对存储器事务的请求。 该方法还包括确定存储器事务是否被授权用于存储位置，并且如果存储器事务被授权用于存储位置，则将存储器事务的请求传递到存储设备。

    Computer system employing a trusted execution environment including a memory controller configured to clear memory
    6.
    发明授权
    Computer system employing a trusted execution environment including a memory controller configured to clear memory 有权
    计算机系统采用可信执行环境，包括配置为清除存储器的存储器控​​制器

    公开(公告)号：US07210009B2

    公开(公告)日：2007-04-24

    申请号：US10654734

    申请日：2003-09-04

    申请人： Dale E. Gulick ,  Geoffrey S. Strongin ,  William A. Hughes

    发明人： Dale E. Gulick ,  Geoffrey S. Strongin ,  William A. Hughes

    IPC分类号： G06F12/12 ,  G06F12/16

    CPC分类号： G06F21/74 ,  G06F21/79 ,  G06F2221/2105 ,  G06F2221/2143

    摘要： A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes a system memory configured to store data in a plurality of locations. The computer system also includes a memory controller which may selectively clear the data from a programmed range of the memory locations of the system memory when enabled in response to a reset of the processor.

    摘要翻译： 计算机系统包括可以通过执行安全初始化指令来初始化安全执行模式的处理器。 此外，处理器可以通过执行安全操作系统代码段在安全执行模式下操作。 计算机系统还包括被配置为在多个位置存储数据的系统存储器。 计算机系统还包括存储器控制器，当响应于处理器的复位使能时，存储器控制器可以选择性地从系统存储器的存储器位置的编程范围中清除数据。

    Method and apparatus for configuring a peripheral bus
    8.
    发明授权
    Method and apparatus for configuring a peripheral bus 有权
    用于配置外围总线的方法和装置

    公开(公告)号：US07162554B1

    公开(公告)日：2007-01-09

    申请号：US09904373

    申请日：2001-07-11

    申请人： Terry Lynn Cole ,  Dale E. Gulick ,  Timothy C. Maleck ,  Frank Barth ,  Joerg Winkler

    发明人： Terry Lynn Cole ,  Dale E. Gulick ,  Timothy C. Maleck ,  Frank Barth ,  Joerg Winkler

    IPC分类号： G06F13/00 ,  G06F3/00

    CPC分类号： G06F13/385

    摘要： A method an apparatus for providing capability information to a shared controller. In one embodiment, a peripheral bus host controller may be shared by a plurality of peripheral devices coupled to a peripheral bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may be configured to query the bus for peripheral devices by reading each address on the bus. During the querying process, the host controller may detect one or more peripheral devices coupled to the bus. Following the completion of the querying of the bus, the host controller may then begin reading configuration information from each of the detected devices. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device. Additional information needed to configure the device to communicate over the peripheral bus may also be obtained with a read of the device, or various lookup mechanisms, such as a lookup table or a tree-like data structure. After configuration information has been obtained for each device coupled to the bus, the host controller may dynamically configure each of the devices for communication over the bus, thereby allowing the flexibility to enumerate riser cards and add new functions through peripheral devices to the computer system in which the bus is implemented.

    摘要翻译： 一种用于向共享控制器提供能力信息的装置的方法。 在一个实施例中，外围总线主机控制器可以由耦合到外围总线的多个外围设备共享。 外围设备可以包括编码器/解码器（编解码器）电路，并且可以使用转接卡来实现。 主机控制器可以被配置为通过读取总线上的每个地址来查询外围设备的总线。 在查询过程期间，主机控制器可以检测耦合到总线的一个或多个外围设备。 在完成对总线的查询之后，主机控制器然后可以开始从每个检测到的设备读取配置信息。 主机控制器可以采用几种不同技术中的一种或多种，​​以便从外围设备读取配置信息。 配置信息至少包括设备标识符，其可以标识供应商和设备的功能。 通过设备的读取或诸如查找表或树状数据结构的各种查找机制也可以获得将设备配置成通过外围总线进行通信所需的附加信息。 在针对耦合到总线的每个设备获得配置信息之后，主机控制器可以动态地配置每个设备以通过总线进行通信，从而允许灵活地枚举转接卡并且通过外围设备将新功能添加到计算机系统 总线实施。

    Serial bus host controller diagnosis
    9.
    发明授权
    Serial bus host controller diagnosis 有权
    串行总线主机控制器诊断

    公开(公告)号：US07131035B2

    公开(公告)日：2006-10-31

    申请号：US10283612

    申请日：2002-10-30

    申请人： Dale E. Gulick ,  Siegfried Kay Hesse

    发明人： Dale E. Gulick ,  Siegfried Kay Hesse

    IPC分类号： G06F11/00

    CPC分类号： G06F11/26

    摘要： A diagnosis mechanism for host controllers such as USB (Universal Serial Bus) host controllers is provided. The host controller has a register set that comprises at least one host controller capability register storing data indicative of operational capabilities of the host controller, and at least one host controller operational register storing data for controlling the operation of the host controller. The at least one host controller capability register stores data that is indicative of available diagnostic modes that the host controller can enter. The at least one host controller operational register stores diagnosis data for controlling the operation of the USB host controller in diagnostic modes. This diagnosis mechanism may improve the reliability of the host controller operation.

    摘要翻译： 提供了诸如USB（通用串行总线）主机控制器的主机控制器的诊断机制。 主机控制器具有寄存器集合，其包括至少一个主机控制器能力寄存器，其存储指示主机控制器的操作能力的数据，以及存储用于控制主机控制器的操作的数据的至少一个主控制器操作寄存器。 至少一个主机控制器能力寄存器存储指示主机控制器可以进入的可用诊断模式的数据。 所述至少一个主机控制器操作寄存器存储用于以诊断模式控制所述USB主机控制器的操作的诊断数据。 该诊断机制可以提高主机控制器操作的可靠性。