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1.发明授权Method and apparatus for a non-deterministic random bit generator (NRBG) 有权用于非确定性随机位发生器（NRBG）的方法和装置公开(公告)号：US09544139B2
公开(公告)日：2017-01-10
申请号：US13976175
申请日：2011-12-29
CPC分类号： H04L9/0869 , G06F7/588 , G06F9/30007 , H04L9/0662 , H04L2209/24
摘要： A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.
摘要翻译： 提供了一种基于硬件的数字随机数发生器。 在一个实施例中，处理器包括数字随机数发生器（DRNG），用于对熵源提供的熵数据进行条件生成，以产生多个确定性随机位（DRB）串，并产生多个非确定性随机位（NRB） 响应于读取种子值的第一指令，从DRNG检索NRB字符串中的一个并将NRB字符串存储在由第一指令指定的目的地寄存器中，耦合到DRNG的执行单元。
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2.发明申请公开(公告)号：US20150055778A1
公开(公告)日：2015-02-26
申请号：US13976175
申请日：2011-12-29
CPC分类号： H04L9/0869 , G06F7/588 , G06F9/30007 , H04L9/0662 , H04L2209/24
摘要： A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.
摘要翻译： 提供了一种基于硬件的数字随机数发生器。 在一个实施例中，处理器包括数字随机数发生器（DRNG），用于对熵源提供的熵数据进行条件生成，以产生多个确定性随机位（DRB）串，并产生多个非确定性随机位（NRB） 响应于读取种子值的第一指令，从DRNG检索NRB字符串中的一个并将NRB字符串存储在由第一指令指定的目的地寄存器中，耦合到DRNG的执行单元。
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公开(公告)号：US08489660B2
公开(公告)日：2013-07-16
申请号：US12459142
申请日：2009-06-26
申请人： Howard C. Herbert , George W. Cox , Shay Gueron , Jesse Walker , Charles E. Dike , Stephen A. Fischer , Ernie Brickell , Martin G. Dixon , David Johnston , Gunendran Thuraisingham , Edward V. Gamsaragan , James S. Coke , Greg W. Piper
发明人： Howard C. Herbert , George W. Cox , Shay Gueron , Jesse Walker , Charles E. Dike , Stephen A. Fischer , Ernie Brickell , Martin G. Dixon , David Johnston , Gunendran Thuraisingham , Edward V. Gamsaragan , James S. Coke , Greg W. Piper
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F9/30007 , H04L9/0861
摘要： A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.
摘要翻译： 提供了一种基于硬件的数字随机数发生器。 数字随机数发生器是基于一组非确定性行为的随机行为随机数发生器。 非确定性行为包括子单元之间的时间不同步，熵源“额外”比特，熵测量，自主确定性随机比特生成器重新获取和来自共享资源的消费。
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公开(公告)号：US20100332574A1
公开(公告)日：2010-12-30
申请号：US12459142
申请日：2009-06-26
申请人： Howard C. Herbert , George W. Cox , Shay Gueron , Jesse Walker , Charles E. Dike , Stephen A. Fischer , Ernie Brickell , Martin G. Dixon , David Johnston , Gunendran Thuraisingham , Edward V. Gamsaragan , James S. Coke , Greg W. Piper
发明人： Howard C. Herbert , George W. Cox , Shay Gueron , Jesse Walker , Charles E. Dike , Stephen A. Fischer , Ernie Brickell , Martin G. Dixon , David Johnston , Gunendran Thuraisingham , Edward V. Gamsaragan , James S. Coke , Greg W. Piper
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F9/30007 , H04L9/0861
摘要： A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.
摘要翻译： 提供了一种基于硬件的数字随机数发生器。 数字随机数发生器是基于一组非确定性行为的随机行为随机数发生器。 非确定性行为包括子单元之间的时间不同步，熵源“额外”比特，熵测量，自主确定性随机比特生成器重新获取和来自共享资源的消费。
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5.发明申请METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRIC CORE VIEW 有权用于打造异质系统并提供对称核心视图的方法公开(公告)号：US20140281457A1
公开(公告)日：2014-09-18
申请号：US13854001
申请日：2013-03-29
申请人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
发明人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
IPC分类号： G06F9/44
CPC分类号： G06F9/4401 , G06F9/45558 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
摘要： A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
摘要翻译： 描述异构处理器架构和启动异构处理器的方法。 根据一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 以及一个包装单元，用于启用自举处理器。 引导处理器初始化同构物理处理器内核，而异构处理器将均匀处理器的外观呈现给系统固件界面。
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公开(公告)号：US09383998B2
公开(公告)日：2016-07-05
申请号：US13440096
申请日：2012-04-05
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
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公开(公告)号：US20140123281A1
公开(公告)日：2014-05-01
申请号：US13664532
申请日：2012-10-31
IPC分类号： G06F21/00
CPC分类号： G06F21/552 , G06F9/30145 , G06F21/566 , G06F2221/034
摘要： In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
摘要翻译： 在一个实施例中，处理器包括至少一个执行单元和返回定向编程（ROP）检测逻辑。 ROP检测逻辑可以基于多个控制传送事件来确定ROP度量。 ROP检测逻辑还可以确定ROP度量是否超过阈值。 ROP检测逻辑还可以响应于ROP度量超过阈值的确定，提供ROP攻击通知。
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公开(公告)号：US08707062B2
公开(公告)日：2014-04-22
申请号：US12706631
申请日：2010-02-16
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，处理器包括第一处理器核心，第二处理器核心和高速缓冲存储器。 第一处理器核心是保存第一处理器核心的状态并进入第一处理器核心断电的模式。 第二处理器核心是保存第二处理器核心的状态并进入其中第二处理器核心断电的模式。 当第一个处理器内核关闭电源时，缓存内存将被供电。 第一处理器核心是响应于第一处理器核心转换到第一处理器核心供电的模式来恢复第一处理器核心的保存状态。 第二处理器核心是响应于第二处理器核心转换到第二处理器核心供电的模式来恢复第二处理器核心的保存状态。 还公开了其他实施例。
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公开(公告)号：US07779239B2
公开(公告)日：2010-08-17
申请号：US10900875
申请日：2004-07-28
CPC分类号： G06F9/30101 , G06F9/30181 , G06F21/629
摘要： A processor includes a feature control unit to enable or disable one or more processor features individually in response to a user selectable setting. The feature control unit is adapted to disable the processor feature(s) if the user setting has not been updated in accordance with an input regardless of the value of the user setting prior to the update and to enable or disable the processor feature(s) in accordance with the updated user setting after it has been updated. The feature control unit may also include a lock unit to prevent changes to the updated user setting and a software feature selection unit to enable or disable processor features in response to a software feature selection setting and, optionally, only enable or disable processor features whose corresponding updated user setting is user enabled. The feature control unit may also include mechanisms to detect illegal feature selection conditions.
摘要翻译： 处理器包括特征控制单元，以响应于用户可选择的设置来单独启用或禁用一个或多个处理器特征。 如果没有根据输入更新用户设置而不考虑更新之前的用户设置的值，并且启用或禁用处理器特征，则特征控制单元适于禁用处理器特征， 根据更新后的用户设置进行更新。 特征控制单元还可以包括用于防止更新的用户设置的改变的锁定单元和软件特征选择单元以响应于软件特征选择设置来启用或禁用处理器特征，并且可选地，仅启用或禁用其相应的处理器特征 更新的用户设置是用户启用的。 特征控制单元还可以包括检测非法特征选择条件的机制。
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10.发明授权Processor unique processor number feature with a user controllable disable capability 有权处理器独特的处理器号码功能，具有用户可控的禁用功能公开(公告)号：US06289459B1
公开(公告)日：2001-09-11
申请号：US09235054
申请日：1999-01-20
IPC分类号： G06F1100
CPC分类号： G06F21/73 , G06F11/006 , G06F21/10 , G06F2207/7219 , G06F2221/0744
摘要： A software method of setting a state in a processor regarding whether a processor number encoded in the processor will be available for reading is described. The method comprises prompting the user to enter an indication whether the processor number should be available for reading by a program. Then, setting a state to inhibit the processor number from being read by a program if the indication indicates that the processor number should not be available for reading by the program. For one embodiment, the method further includes testing the indication if a request for the processor number is received, and releasing the processor number if the indication indicates that the processor number is available.
摘要翻译： 描述了在处理器中设置处理器中编码的处理器编号是否可用于读取的状态的软件方法。 该方法包括提示用户输入处理器号码是否应可供程序读取的指示。 然后，如果该指示指示处理器号码不可用于程序读取，则设置状态以阻止处理器号码被程序读取。 对于一个实施例，所述方法还包括：如果接收到对所述处理器号码的请求，则测试所述指示，以及如果所述指示指示所述处理器号码可用则释放所述处理器号码。
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