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    Nitrided STI liner oxide for reduced corner device impact on vertical device performance
    4.
    发明授权
    Nitrided STI liner oxide for reduced corner device impact on vertical device performance 有权
    氮化氮化物衬垫氧化物，用于减少拐角装置对垂直装置性能的影响

    公开(公告)号：US06998666B2

    公开(公告)日：2006-02-14

    申请号：US10707754

    申请日：2004-01-09

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

    摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.

    摘要翻译： 一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极 导体和掺硼通道。 该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。 然后在DRAM单元的两侧的沟槽中形成隔离区。 此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。 与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

    Filling high aspect ratio isolation structures with polysilazane based material
    5.
    发明授权
    Filling high aspect ratio isolation structures with polysilazane based material 失效
    用聚硅氮烷基材料填充高纵横比隔离结构

    公开(公告)号：US06869860B2

    公开(公告)日：2005-03-22

    申请号：US10250092

    申请日：2003-06-03

    申请人： Michael P. Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth T. Settlemeyer, Jr. ,  Padraic C. Shafer

    发明人： Michael P. Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth T. Settlemeyer, Jr. ,  Padraic C. Shafer

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L21/76229

    摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

    摘要翻译： 包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率 通过HDP技术，并且耐用性足以承受CMP抛光。

    Filling high aspect ratio isolation structures with polysilazane based material
    7.
    发明申请
    Filling high aspect ratio isolation structures with polysilazane based material 审中-公开
    用聚硅氮烷基材料填充高纵横比隔离结构

    公开(公告)号：US20050179112A1

    公开(公告)日：2005-08-18

    申请号：US11035392

    申请日：2005-01-12

    申请人： Michael Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth Settlemyer ,  Padraic Shafer

    发明人： Michael Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth Settlemyer ,  Padraic Shafer

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L21/76229

    摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H20 ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

    摘要翻译： 包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率 通过HDP技术，并且耐用性足以承受CMP抛光。

    Pitcher-shaped active area for field effect transistor and method of forming same
    8.
    发明授权
    Pitcher-shaped active area for field effect transistor and method of forming same 失效
    投币型场效应晶体管及其形成方法

    公开(公告)号：US06960514B2

    公开(公告)日：2005-11-01

    申请号：US10803395

    申请日：2004-03-18

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224

    摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

    摘要翻译： 对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。 投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。 还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部 区域结构。 本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

    NITRIDED STI LINER OXIDE FOR REDUCED CORNER DEVICE IMPACT ON VERTICAL DEVICE PERFORMANCE
    9.
    发明申请
    NITRIDED STI LINER OXIDE FOR REDUCED CORNER DEVICE IMPACT ON VERTICAL DEVICE PERFORMANCE 有权
    用于减少角膜器件的氮化硅氧化物对垂直器件性能的影响

    公开(公告)号：US20050151181A1

    公开(公告)日：2005-07-14

    申请号：US10707754

    申请日：2004-01-09

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

    IPC分类号： H01L21/8242 ,  H01L21/762 ,  H01L27/108 ,  H01L29/76

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

    摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.

    摘要翻译： 一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极 导体和掺硼通道。 该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。 然后在DRAM单元的两侧的沟槽中形成隔离区。 此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。 与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。