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公开(公告)号：US09042557B2
公开(公告)日：2015-05-26
申请号：US13452260
申请日：2012-04-20
Applicant: Jeong Il Seo , Jae Hyoun Yoo , Kyeong Ok Kang , Min Cheol Shin , Filippo M Fazi , Philip A. Nelson
Inventor： Jeong Il Seo , Jae Hyoun Yoo , Kyeong Ok Kang , Min Cheol Shin , Filippo M Fazi , Philip A. Nelson
CPC classification number: H04S3/006
Abstract: Provided is a method and apparatus for reproducing a three-dimensional (3D) sound field. A method of reproducing a 3D sound field may determine a control region based on a wavelength of an excitation frequency, set, based on a loudspeaker array, at least one candidate control point in the control region, and determine a non-uniform control point corresponding to a non-uniform loudspeaker.
Abstract translation: 提供了一种用于再现三维（3D）声场的方法和装置。 再现3D声场的方法可以基于基于扬声器阵列，至少一个控制区域中的候选控制点设置的激励频率的波长来确定控制区域，并且确定相应的不均匀的控制点 到不均匀的扬声器。
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2.发明授权Negative capacitance logic device, clock generator including the same and method of operating clock generator 有权负电容逻辑器件，时钟发生器包括相同的操作时钟发生器和方法公开(公告)号：US09484924B2
公开(公告)日：2016-11-01
申请号：US14614884
申请日：2015-02-05
Applicant: Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
Inventor： Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
IPC: H03K3/315 , H03L7/26 , H03K19/16 , H03K19/0185 , H03B15/00 , H01L29/66 , B82Y25/00 , H01L43/02 , G11C11/16 , H01L43/10
CPC classification number: H03K19/16 , B82Y25/00 , G11C11/16 , H01L29/66984 , H01L43/02 , H01L43/08 , H01L43/10 , H03B15/006 , H03K19/018578
Abstract: A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.
Abstract translation: 负电容逻辑器件包括第一场效应晶体管（FET）和第二FET。 第一FET耦合在电源电压和输出节点之间，并且第一FET包括具有负电容的铁电体。 第二FET耦合在输出节点和接地电压之间，第二FET包括具有负电容的铁电体。 负电容逻辑区分施加到输入节点的输入电压以在输出节点处提供输出电压。
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公开(公告)号：US08712079B2
公开(公告)日：2014-04-29
申请号：US12507364
申请日：2009-07-22
Applicant: Hye Jin Kim , Sung Q Lee , Min Cheol Shin , Kang Ho Park , Jong Dae Kim
Inventor： Hye Jin Kim , Sung Q Lee , Min Cheol Shin , Kang Ho Park , Jong Dae Kim
CPC classification number: H04R17/00 , H04R1/06 , H04R31/006 , H04R2499/11
Abstract: A piezoelectric speaker and a method of manufacturing the same that can obtain a high sound pressure using a piezoelectric thin film are provided. The piezoelectric speaker includes a piezoelectric thin film, electrodes formed on an upper surface or upper and lower surfaces of the piezoelectric thin film, a damping material layer formed on the lower surface of the piezoelectric thin film, and a frame attached around at least one of the piezoelectric thin film and the damping material layer using an adhesive.
Abstract translation: 提供一种使用压电薄膜可以获得高声压的压电扬声器及其制造方法。 压电扬声器包括压电薄膜，形成在压电薄膜的上表面或上表面和下表面上的电极，形成在压电薄膜的下表面上的阻尼材料层和围绕至少一个 压电薄膜和使用粘合剂的阻尼材料层。
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公开(公告)号：US5994714A
公开(公告)日：1999-11-30
申请号：US932189
申请日：1997-09-17
Applicant: Kyoung Wan Park , Seong Jae Lee , Min Cheol Shin
Inventor： Kyoung Wan Park , Seong Jae Lee , Min Cheol Shin
IPC: H01L29/06 , H01L21/335 , H01L29/66 , H01L29/772 , H01L29/80 , H01L29/775 , H01L29/778
CPC classification number: B82Y10/00 , H01L29/66446 , H01L29/66977 , H01L29/772 , Y10S438/962
Abstract: The present invention discloses a technique for applying diffraction characteristic of electrons to a two-dimensional electronic device to manufacture multi-functional transistor having various ON/OFF states. A quantum diffraction transistor according to the present invention is capable of adjusting the amplitude of drain current and having various ON/OFF states utilizing diffraction characteristic of electrons by interposing a reflection-type diffraction grating in an electron path. The inventive multi-functional quantum diffraction transistor uses a two dimensional electron gas in formed at a different species junction in a semiconductor heterostructure, and has a bent electron path between the source electrode and the drain electrode with a reflection-type diffraction grating. The quantum diffraction effect of the electrons is used for the control of the diffracted drain current.
Abstract translation: 本发明公开了一种将电子衍射特性应用于二维电子器件以制造具有各种ON / OFF状态的多功能晶体管的技术。 根据本发明的量子衍射晶体管能够通过在电子路径中插入反射型衍射光栅来利用电子的衍射特性来调节漏极电流的振幅并具有各种导通/截止状态。 本发明的多功能量子衍射晶体管使用在半导体异质结构中的不同物质结处形成的二维电子气体，并且在反射型衍射光栅之间具有在源电极和漏电极之间的弯曲电子路径。 电子的量子衍射效应用于衍射漏极电流的控制。
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公开(公告)号：US06812985B1
公开(公告)日：2004-11-02
申请号：US09536629
申请日：2000-03-28
Applicant: Young Jin Oh , Kyoung Nam Lim , Dong Hyo Gu , Sang Ho Lee , Min Cheol Shin
Inventor： Young Jin Oh , Kyoung Nam Lim , Dong Hyo Gu , Sang Ho Lee , Min Cheol Shin
IPC: G02F113
CPC classification number: G02F1/134363 , G02F2001/136218
Abstract: A liquid crystal display device includes a first substrate including a plurality of data bus lines, a plurality of gate bus lines, and a plurality of thin film transistors at cross points of the plurality gate bus lines and the plurality of gate bus lines; a second substrate including a color filter layer; at least one shielding layer for shielding an outer induced electric field; and a liquid crystal layer sandwiched between the first substrate and the second substrate.
Abstract translation: 液晶显示装置包括在多个栅极总线和多个栅极总线的交叉点处包括多个数据总线，多个栅极总线和多个薄膜晶体管的第一基板; 包括滤色器层的第二基板; 用于屏蔽外部感应电场的至少一个屏蔽层; 以及夹在第一基板和第二基板之间的液晶层。
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Patent Agency Ranking
公开(公告)号：US06462727B2
公开(公告)日：2002-10-08
申请号：US09982872
申请日：2001-10-22
Applicant: Min Cheol Shin
Inventor： Min Cheol Shin
IPC: G09G336
CPC classification number: G09G3/3688 , G09G3/3666 , G09G5/18 , G09G2352/00
Abstract: A driving circuit for driving a liquid crystal display is provided. The driving circuit includes a clock generator processing a first clock signal to output a second clock signal, the clock speed of the second clock signal being half of that of the first clock signal, a memory for storing a first video data and a second video data in accordance with the first clock signal, and a data controller for simultaneously outputting the first video data and the second video data stored in the memory in accordance with the second clock signal.
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公开(公告)号：US6037198A
公开(公告)日：2000-03-14
申请号：US139651
申请日：1998-08-25
Applicant: Kyoung Wan Park , Seong Jae Lee , Moon Ho Park , Min Cheol Shin , Sang Chul Oh
Inventor： Kyoung Wan Park , Seong Jae Lee , Moon Ho Park , Min Cheol Shin , Sang Chul Oh
IPC: H01L21/20 , H01L21/762 , H01C71/00
CPC classification number: H01L21/76262
Abstract: The present invention is to fabricate SOI wafer whose the silicon layer is very uniform and the impurity concentration is low. The insulating layer, that is, a composite layer of SiO2 and silicon, is grown on oxide substrate by means of a molecular beam epitaxy fabricating method using silicon as an original material in the oxygen atmosphere. The composite layer of the oxide and silicon is grown according to gradual decreasing the pressure of oxygen atmosphere. A top silicon layer of uniform thickness is grown by means of a molecular beam epitaxy fabricating method using only silicon material consecutively on the composite layer.
Abstract translation: 本发明是制造硅层非常均匀且杂质浓度低的SOI晶片。 通过在氧气氛中使用硅作为原料的分子束外延制造方法，在氧化物衬底上生长绝缘层，即SiO 2和硅的复合层。 氧化物和硅的复合层根据氧气气氛的逐渐降低而生长。 通过在复合层上连续使用硅材料的分子束外延制造方法生长均匀厚度的顶部硅层。
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公开(公告)号：US5940696A
公开(公告)日：1999-08-17
申请号：US932616
申请日：1997-09-17
Applicant: Kyoung Wan Park , Seong Jae Lee , Min Cheol Shin
Inventor： Kyoung Wan Park , Seong Jae Lee , Min Cheol Shin
IPC: H01L29/06 , H01L21/335 , H01L29/66 , H01L29/772 , H01L29/80 , H01L21/338
CPC classification number: B82Y10/00 , H01L29/66446 , H01L29/66977 , H01L29/772 , Y10S438/962
Abstract: The present invention discloses a technique for applying diffraction characteristics of electrons to a two-dimensional electronic device to manufacture multi-functional transistor having various ON/OFF states. Method of manufacturing a quantum diffraction transistor according to the present invention is capable of adjusting the amplitude of drain current and having various ON/OFF states utilizing diffraction characteristics of electrons by interposing a reflection-type diffraction grating in a bent electron path. In the inventive multi-functional quantum diffraction transistor using a two dimensional electron gas in quantum well structure formed at a different species junction in a heterostructure semiconductor device and having a bent electron path between the source electrode and the drain electrode with a reflection-type diffraction grating, the quantum diffraction effect of the electrons is used for the control of the diffracted drain current.
Abstract translation: 本发明公开了一种将电子衍射特性应用于二维电子器件以制造具有各种ON / OFF状态的多功能晶体管的技术。 根据本发明的量子衍射晶体管的制造方法能够通过在弯曲的电子路径中插入反射型衍射光栅来利用电子的衍射特性来调节漏极电流的振幅并具有各种导通/截止状态。 在本发明的多功能量子衍射晶体管中，使用在异质结构半导体器件中形成于不同物质结的量子阱结构中的二维电子气，并且在源电极和漏电极之间具有反射型衍射 光栅，电子的量子衍射效应用于衍射漏极电流的控制。
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9.发明申请NEGATIVE CAPACITANCE LOGIC DEVICE, CLOCK GENERATOR INCLUDING THE SAME AND METHOD OF OPERATING CLOCK GENERATOR 有权负电容逻辑器件，包括其的时钟发生器和操作时钟发生器的方法公开(公告)号：US20160211849A1
公开(公告)日：2016-07-21
申请号：US14614884
申请日：2015-02-05
Applicant: Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
Inventor： Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
IPC: H03K19/16 , H03L7/26 , H03B15/00 , H03K19/0185
CPC classification number: H03K19/16 , B82Y25/00 , G11C11/16 , H01L29/66984 , H01L43/02 , H01L43/08 , H01L43/10 , H03B15/006 , H03K19/018578
Abstract: A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.
Abstract translation: 负电容逻辑器件包括第一场效应晶体管（FET）和第二FET。 第一FET耦合在电源电压和输出节点之间，并且第一FET包括具有负电容的铁电体。 第二FET耦合在输出节点和接地电压之间，第二FET包括具有负电容的铁电体。 负电容逻辑区分施加到输入节点的输入电压以在输出节点处提供输出电压。
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公开(公告)号：US20100158283A1
公开(公告)日：2010-06-24
申请号：US12507364
申请日：2009-07-22
Applicant: Hye Jin Kim , Sung Q. Lee , Min Cheol Shin , Kang Ho Park , Jong Dae Kim
Inventor： Hye Jin Kim , Sung Q. Lee , Min Cheol Shin , Kang Ho Park , Jong Dae Kim
CPC classification number: H04R17/00 , H04R1/06 , H04R31/006 , H04R2499/11
Abstract: A piezoelectric speaker and a method of manufacturing the same that can obtain a high sound pressure using a piezoelectric thin film are provided. The piezoelectric speaker includes a piezoelectric thin film, electrodes formed on an upper surface or upper and lower surfaces of the piezoelectric thin film, a damping material layer formed on the lower surface of the piezoelectric thin film, and a frame attached around at least one of the piezoelectric thin film and the damping material layer using an adhesive.
Abstract translation: 提供一种使用压电薄膜可以获得高声压的压电扬声器及其制造方法。 压电扬声器包括压电薄膜，形成在压电薄膜的上表面或上表面和下表面上的电极，形成在压电薄膜的下表面上的阻尼材料层和围绕至少一个 压电薄膜和使用粘合剂的阻尼材料层。
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