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1.发明申请Novel structure for reducing low-k dielectric damage and improving copper EM performance 审中-公开用于降低低k电介质损伤和提高铜电感性能的新型结构公开(公告)号：US20080258303A1
公开(公告)日：2008-10-23
申请号：US11788986
申请日：2007-04-23
申请人： Ming-Shih Yeh , Tien-I Bao , David Ding-Chung Lu
发明人： Ming-Shih Yeh , Tien-I Bao , David Ding-Chung Lu
IPC分类号： H01L23/528 , H01L21/44
CPC分类号： H01L21/7684 , H01L21/288 , H01L21/76829 , H01L21/76834 , H01L21/76849
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a dielectric layer; a chemical mechanical polish (CMP) stop layer on the dielectric layer; a conductive wiring in the dielectric layer; and a metal cap over the conductive wiring.
摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括电介质层; 电介质层上的化学机械抛光（CMP）停止层; 电介质层中的导电布线; 和导电布线上的金属盖。
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公开(公告)号：US08053865B2
公开(公告)日：2011-11-08
申请号：US12045547
申请日：2008-03-10
IPC分类号： H01L29/72
CPC分类号： H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure combining air-gaps and metal-oxide-metal (MOM) capacitors is provided. The integrated circuit structure includes a semiconductor substrate; a first metallization layer over the semiconductor substrate; first metal features in the first metallization layer; a second metallization layer over the first metallization layer; second metal features in the second metallization layer, wherein the first and the second metal features are non-capacitor features; a MOM capacitor having an area in at least one of the first and the second metallization layers; and an air-gap in the first metallization layer and between the first metal features.
摘要翻译： 提供了一种组合气隙和金属氧化物金属（MOM）电容器的集成电路结构。 集成电路结构包括半导体衬底; 半导体衬底上的第一金属化层; 第一金属层中的第一金属特征; 第一金属化层上的第二金属化层; 在第二金属化层中的第二金属特征，其中第一和第二金属特征是非电容器特征; MOM电容器，其具有在所述第一和第二金属化层中的至少一个中的区域; 以及在第一金属化层中和第一金属特征之间的气隙。
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公开(公告)号：US20120090547A1
公开(公告)日：2012-04-19
申请号：US13337846
申请日：2011-12-27
IPC分类号： C23C16/46
CPC分类号： H01L21/0273 , B05D1/60 , B05D3/02 , G03F7/167 , H01L21/0276
摘要： Provided is a system for vapor deposition of a coating material onto a semiconductor substrate. The system includes a chemical supply chamber, a supply nozzle operable to dispense vapor, and a heating element operable to provide heat to a substrate in-situ with the dispensing of vapor. The system may further include reaction chamber(s) and/or mixing chamber(s).
摘要翻译： 提供了一种用于将涂料气相沉积到半导体衬底上的系统。 该系统包括化学品供应室，可操作以分配蒸气的供应喷嘴和可操作以随着蒸汽分配而原位向基板提供热量的加热元件。 该系统可以进一步包括反应室和/或混合室。
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公开(公告)号：US08105954B2
公开(公告)日：2012-01-31
申请号：US12254658
申请日：2008-10-20
IPC分类号： H01L21/47
CPC分类号： H01L21/0273 , B05D1/60 , B05D3/02 , G03F7/167 , H01L21/0276
摘要： Provided is a method and system for vapor deposition of a coating material onto a semiconductor substrate. In an embodiment, photoresist is deposited. An in-situ baking process may be performed with the vapor deposition. In an embodiment, a ratio of chemical components of a material to be deposited onto the substrate is changed during the deposition. Therefore, a layer having a gradient chemical component distribution may be provided. In an embodiment, a BARC layer may be provided which includes a gradient chemical component distribution providing an n,k distribution through the layer. Other materials that may be vapor deposited include pattern freezing material.
摘要翻译： 提供了一种用于将涂料气相沉积到半导体衬底上的方法和系统。 在一个实施例中，沉积光致抗蚀剂。 可以通过气相沉积来进行原位烘烤工艺。 在一个实施例中，在沉积期间改变待沉积到衬底上的材料的化学成分的比例。 因此，可以提供具有梯度化学成分分布的层。 在一个实施例中，可以提供BARC层，其包括提供通过该层的n，k分布的梯度化学分量分布。 可能蒸气沉积的其他材料包括图案冷冻材料。
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公开(公告)号：US20090136876A1
公开(公告)日：2009-05-28
申请号：US12362316
申请日：2009-01-29
IPC分类号： G03F7/20
CPC分类号： G03F7/70341 , G03F7/203 , G03F7/70466
摘要： A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lower-precision lithography mechanism. The exposures can be done in either order, and additional exposures can be included. The higher-precision lithography mechanism can be immersion lithography and the lower-precision lithography mechanism can be dry lithography.
摘要翻译： 用于在衬底上产生图案的方法包括通过更高精度的光刻机构将图案的至少一次曝光提供到衬底的层上，并且通过较低精度的光刻机提供图案的至少一次曝光到衬底的层上， 精密光刻机制。 曝光可以以任一顺序完成，并可以包括额外的曝光。 高精度光刻机构可以是浸没式光刻技术，较低精度的光刻机构可以是干式光刻技术。
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公开(公告)号：US08134235B2
公开(公告)日：2012-03-13
申请号：US11788974
申请日：2007-04-23
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/30604 , H01L21/76898 , H01L24/03 , H01L24/09 , H01L24/48 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/031 , H01L2224/0331 , H01L2224/0355 , H01L2224/05553 , H01L2224/08113 , H01L2224/08135 , H01L2224/48091 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06544 , H01L2225/06548 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.
摘要翻译： 一种使用冗余接合导体结构的三维半导体器件，用于在多个半导体芯片之间进行层间电连接。 第一芯片或其它半导体衬底在其上表面上形成第一有源区，并且第二芯片或其它半导体衬底在其上表面上形成第二有源区。 根据本发明，当第二芯片已经被安装在第一芯片上方面向上或向下时，第一有效区域通过至少一个冗余结合导体结构耦合到第二有源区域。 在一个实施例中，每个冗余接合导体结构包括至少一个贯穿第二芯片的至少一个通孔部分，以执行该功能。 另一方面，冗余接合导体结构向下延伸到顶层互连。 本发明还包括制造这种装置的方法。
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公开(公告)号：US20090090951A1
公开(公告)日：2009-04-09
申请号：US11868856
申请日：2007-10-08
申请人： Chung-Long Chang , David Ding-Chung Lu , Chia-Yi Chen , I-Lu Wu
发明人： Chung-Long Chang , David Ding-Chung Lu , Chia-Yi Chen , I-Lu Wu
IPC分类号： H01L27/108
CPC分类号： H01L27/11568 , H01L23/5223 , H01L27/0629 , H01L27/105 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.
摘要翻译： 提供了包括具有增加的电容和改善的电性能的电容器的半导体结构。 半导体结构包括基板; 以及在基板上的电容器。 电容器包括：第一层，包括第一电容器电极和第二电容器电极，其中第一电容器电极由含金属的材料形成并且不含多晶硅。 所述半导体结构还包括：在所述基板上包括栅电介质的MOS器件; 以及栅极电介质上的含金属的栅电极，其中所述含金属的栅电极由与所述第一电容器电极相同的材料形成，并且具有相同的厚度。
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公开(公告)号：US07501227B2
公开(公告)日：2009-03-10
申请号：US11216658
申请日：2005-08-31
IPC分类号： G03F7/20
CPC分类号： G03F7/70341 , G03F7/203 , G03F7/70466
摘要： A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lower-precision lithography mechanism. The exposures can be done in either order, and additional exposures can be included. The higher-precision lithography mechanism can be immersion lithography and the lower-precision lithography mechanism can be dry lithography.
摘要翻译： 用于在衬底上产生图案的方法包括通过更高精度的光刻机构将图案的至少一次曝光提供到衬底的层上，并且通过较低精度的光刻机提供图案的至少一次曝光到衬底的层上， 精密光刻机制。 曝光可以以任一顺序完成，并可以包括额外的曝光。 高精度光刻机构可以是浸没式光刻技术，较低精度的光刻机构可以是干式光刻技术。
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公开(公告)号：US20120164789A1
公开(公告)日：2012-06-28
申请号：US13417917
申请日：2012-03-12
IPC分类号： H01L21/60
CPC分类号： H01L23/481 , H01L21/30604 , H01L21/76898 , H01L24/03 , H01L24/09 , H01L24/48 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/031 , H01L2224/0331 , H01L2224/0355 , H01L2224/05553 , H01L2224/08113 , H01L2224/08135 , H01L2224/48091 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06544 , H01L2225/06548 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.
摘要翻译： 公开了一种使用冗余接合导体结构在多个半导体芯片之间进行层间电连接的三维半导体器件。 第一芯片或其它半导体衬底在其上表面上形成第一有源区，并且第二芯片或其它半导体衬底在其上表面上形成第二有源区。 根据本发明，当第二芯片已经安装在第一芯片上方面向上或者朝下时，第一有源区域通过至少一个冗余结合导体结构耦合到第二有源区域。 在一个实施例中，每个冗余接合导体结构包括至少一个贯穿第二芯片的至少一个通孔部分，以执行该功能。 另一方面，冗余接合导体结构向下延伸到顶层互连。 本发明还包括制造这种装置的方法。
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公开(公告)号：US20090224359A1
公开(公告)日：2009-09-10
申请号：US12045547
申请日：2008-03-10
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure combining air-gaps and metal-oxide-metal (MOM) capacitors is provided. The integrated circuit structure includes a semiconductor substrate; a first metallization layer over the semiconductor substrate; first metal features in the first metallization layer; a second metallization layer over the first metallization layer; second metal features in the second metallization layer, wherein the first and the second metal features are non-capacitor features; a MOM capacitor having an area in at least one of the first and the second metallization layers; and an air-gap in the first metallization layer and between the first metal features.
摘要翻译： 提供了一种组合气隙和金属氧化物金属（MOM）电容器的集成电路结构。 集成电路结构包括半导体衬底; 半导体衬底上的第一金属化层; 第一金属层中的第一金属特征; 第一金属化层上的第二金属化层; 在第二金属化层中的第二金属特征，其中第一和第二金属特征是非电容器特征; MOM电容器，其具有在所述第一和第二金属化层中的至少一个中的区域; 以及在第一金属化层中和第一金属特征之间的气隙。
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