利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.025 秒)

    LIQUID CRYSTAL DISPLAY HAVING A HIGH APERTURE RATIO
    6.
    发明申请
    LIQUID CRYSTAL DISPLAY HAVING A HIGH APERTURE RATIO 审中-公开
    具有高孔径比的液晶显示

    公开(公告)号：US20130099238A1

    公开(公告)日：2013-04-25

    申请号：US13467047

    申请日：2012-05-09

    申请人： Ming-Yao Chen ,  Pei-Ming Chen

    发明人： Ming-Yao Chen ,  Pei-Ming Chen

    IPC分类号： H01L29/786

    CPC分类号： G02F1/13471 ,  G02F1/1362 ,  H01L27/1225

    摘要： A (liquid crystal display) LCD includes a pixel array and a gate driving circuit. The pixel array includes a plurality of first oxide thin film transistors, a first oxide thin film transistor of the first oxide thin film transistors with a shortest channel length having a first channel length. The gate driving circuit is coupled to the pixel array for driving the pixel array, and includes a plurality of second oxide thin film transistors. The second oxide thin film of the second oxide thin film transistors with a longest channel length has a second channel length. A ratio of the second channel length and the first channel length is greater than 1.5. By limiting the ratio of the second channel length and the first channel length, the aperture ratio of the display panel can be improved without deteriorating the operation stability of the LCD.

    摘要翻译： A（液晶显示器）LCD包括像素阵列和栅极驱动电路。 像素阵列包括多个第一氧化物薄膜晶体管，具有第一沟道长度的具有最短沟道长度的第一氧化物薄膜晶体管的第一氧化物薄膜晶体管。 栅极驱动电路耦合到像素阵列以驱动像素阵列，并且包括多个第二氧化物薄膜晶体管。 具有最长沟道长度的第二氧化物薄膜晶体管的第二氧化物薄膜具有第二沟道长度。 第二通道长度与第一通道长度之比大于1.5。 通过限制第二通道长度和第一通道长度的比例，可以提高显示面板的开口率，而不会降低LCD的操作稳定性。

    Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips
    7.
    发明授权
    Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips 有权
    具有TSV（通过硅通孔）和包括芯片的堆叠组件的半导体芯片

    公开(公告)号：US07838967B2

    公开(公告)日：2010-11-23

    申请号：US12108903

    申请日：2008-04-24

    申请人： Ming-Yao Chen

    发明人： Ming-Yao Chen

    IPC分类号： H01L23/488

    CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/08245 ,  H01L2224/80141 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

    摘要： A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and second bonding pads. By forming first extruded ring, the first bonding pad has a first contact surface located between the first extruded ring and the through hole. By forming second extruded ring, the second bonding pad has a second contact surface located outside and adjacent to the second extruded rings to encircle the second extruded ring. The second extruded ring has a proper dimension to fit in the first extruded ring. Accordingly, a plurality of semiconductor chip can be stacked each other with accurate alignment without shifting to effectively reduce the stacked assembly height, moreover, chip stacking processes are accomplished by vertically stacking a plurality of chips first then filling conductive material into the through holes without electrical short between the adjacent bonding pads due to overflow of conductive material to meet the fine-pitch requirements of TSV. The process flow for the stacked assembly is simplified with higher production yields.

    摘要翻译： 揭示了通过硅通孔（TSV）的半导体芯片和包括芯片的堆叠组件。 芯片具有分别设置在半导体衬底的两个相对表面上的多个第一和第二接合焊盘。 通孔垂直地穿过半导体衬底和第一和第二焊盘。 通过形成第一挤压环，第一接合焊盘具有位于第一挤压环和通孔之间的第一接触表面。 通过形成第二挤压环，第二接合焊盘具有位于第二挤压环的外侧并与第二挤压环相邻的第二接触表面，以环绕第二挤压环。 第二挤压环具有适合尺寸以适合第一挤出环。 因此，可以精确地对准多个半导体芯片，而不需要移位，从而有效地降低堆叠的组装高度，此外，首先通过垂直堆叠多个芯片，然后将导电材料填充到通孔中而不用电 由于导电材料溢出而导致相邻焊盘之间短路，以满足TSV的精细间距要求。 叠层组件的工艺流程可以通过更高的生产率得到简化。