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1.发明授权
公开(公告)号：US5870337A
公开(公告)日：1999-02-09
申请号：US986575
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译： 闪存可擦除半导体存储器件具有存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制 电路提供写入控制信号时，写入信息。 写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。 此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。
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公开(公告)号：US5761127A
公开(公告)日：1998-06-02
申请号：US978976
申请日：1992-11-20
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
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公开(公告)号：US5835408A
公开(公告)日：1998-11-10
申请号：US985714
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
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4.发明授权
公开(公告)号：US6014329A
公开(公告)日：2000-01-11
申请号：US986337
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译： 闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制 电路提供写入控制信号时，写入信息。 写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。 此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。
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5.发明授权
公开(公告)号：US5910916A
公开(公告)日：1999-06-08
申请号：US986339
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/00
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译： 闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制 电路提供写入控制信号时，写入信息。 写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。 此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。
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公开(公告)号：US5835416A
公开(公告)日：1998-11-10
申请号：US986338
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/00
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
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公开(公告)号：US5590074A
公开(公告)日：1996-12-31
申请号：US466732
申请日：1995-06-06
CPC分类号： G11C16/30 , G11C16/26 , G11C29/04 , G06F2201/81
摘要： A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (Vcc), the gate of the transistor being connected to a low source voltage (Vss) to provide an internal source voltage (Vci), a combination of an arrangement for dropping the external source voltage (Vcc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (Vref) as a lower threshold (Vth) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (Vref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.
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公开(公告)号：US5770963A
公开(公告)日：1998-06-23
申请号：US436699
申请日：1995-05-08
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21 , H03K5/08
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： A flash memory performs channel erasing or source erasing by applying a negative voltage to a control gate. The device includes a voltage restriction device which restricts the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of the channel or source. Alternatively, two voltage restricting devices restrict the negative voltage applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.
摘要翻译： 闪存通过向控制栅极施加负电压来执行信道擦除或源擦除。 该装置包括限制施加到控制栅极的负电压的电压限制装置，使得负电压相对于通道或源的电压将是恒定值。 或者，两个电压限制装置限制施加到控制栅极的负电压和施加到源极的电压，使得电压相对于公共参考电压将是恒定值。
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公开(公告)号：US5592419A
公开(公告)日：1997-01-07
申请号：US441598
申请日：1995-05-15
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.
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公开(公告)号：US5572463A
公开(公告)日：1996-11-05
申请号：US416281
申请日：1995-04-04
CPC分类号： G11C16/30 , G11C16/26 , G11C29/04 , G06F2201/81
摘要： A semiconductor memory having address buffer means, memory cell means, word line selection means, bit line selection means, an output buffer, first address generation means connected to the address buffer means, for providing and address for specifying a group of data pieces, and second address generation means for providing addresses for specifying the data pieces, respectively, the semiconductor memory comprising first reading means for selecting and reading a group of data pieces through one of the word line selection means and bit line selection means according to an address provided by the first address generation means, second reading means for selecting the data pieces, which have been selected and read according to the address provided by the first address generation means, through one of the bit line selection means and word line selection means according addresses provided by the second address generation means and providing them to the output buffer; and pre-reading means for reading another group of data pieces according the another address to be provided by the first address generation means while the preceding data pieces are being read according to the preceding address provided by the first address generation means and being selectively provided to the output buffer according to the addresses provided by the second address generation means.
摘要翻译： 具有地址缓冲器装置，存储单元装置，字线选择装置，位线选择装置，输出缓冲器，连接到地址缓冲器装置的第一地址产生装置的半导体存储器，用于提供和寻址用于指定一组数据片段，以及 第二地址产生装置，分别提供用于指定数据片段的地址，所述半导体存储器包括第一读取装置，用于根据由字线选择装置和位线选择装置中的一个选择和读取一组数据片段， 第一地址产生装置，用于根据由第一地址产生装置提供的地址选择和读取的数据片段的第二地址产生装置，通过位线选择装置和字线选择装置之一，根据由 第二地址产生装置并将其提供给输出缓冲器; 以及预读取装置，用于根据由第一地址产生装置提供的另一地址读取另一组数据片段，同时根据由第一地址产生装置提供的先前地址读取先前的数据，并且选择性地提供给 所述输出缓冲器根据由所述第二地址产生装置提供的地址。
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