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公开(公告)号：US5835408A
公开(公告)日：1998-11-10
申请号：US985714
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
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2.发明授权
公开(公告)号：US5870337A
公开(公告)日：1999-02-09
申请号：US986575
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译： 闪存可擦除半导体存储器件具有存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制 电路提供写入控制信号时，写入信息。 写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。 此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。
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公开(公告)号：US5761127A
公开(公告)日：1998-06-02
申请号：US978976
申请日：1992-11-20
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
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4.发明授权
公开(公告)号：US5910916A
公开(公告)日：1999-06-08
申请号：US986339
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/00
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译： 闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制 电路提供写入控制信号时，写入信息。 写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。 此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。
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公开(公告)号：US5835416A
公开(公告)日：1998-11-10
申请号：US986338
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/00
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
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6.发明授权
公开(公告)号：US6014329A
公开(公告)日：2000-01-11
申请号：US986337
申请日：1997-12-05
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译： 闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制 电路提供写入控制信号时，写入信息。 写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。 此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。
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公开(公告)号：US20060228899A1
公开(公告)日：2006-10-12
申请号：US11441237
申请日：2006-05-26
申请人： Hiroyuki Nansei , Manabu Nakamura , Kentaro Sera , Masahiko Higashi , Yukihiro Utsuno , Hideo Takagi , Tatsuya Kajita
发明人： Hiroyuki Nansei , Manabu Nakamura , Kentaro Sera , Masahiko Higashi , Yukihiro Utsuno , Hideo Takagi , Tatsuya Kajita
IPC分类号： H01L21/31 , H01L21/336
CPC分类号： H01L21/0234 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02326 , H01L21/02332 , H01L21/3145 , H01L27/105 , H01L27/11526 , H01L27/11546 , H01L27/11568 , Y10S438/954
摘要： After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.
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8.发明授权公开(公告)号：US07098147B2
公开(公告)日：2006-08-29
申请号：US10643967
申请日：2003-08-20
申请人： Hiroyuki Nansei , Manabu Nakamura , Kentaro Sera , Masahiko Higashi , Yukihiro Utsuno , Hideo Takagi , Tatsuya Kajita
发明人： Hiroyuki Nansei , Manabu Nakamura , Kentaro Sera , Masahiko Higashi , Yukihiro Utsuno , Hideo Takagi , Tatsuya Kajita
IPC分类号： H01L21/31
CPC分类号： H01L27/11568 , H01L21/3145 , H01L27/105 , H01L27/11526 , H01L27/11546 , Y10S438/954
摘要： After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.
摘要翻译： 在硅区域上形成下部氧化硅膜之后，通过例如热CVD法在下部氧化硅膜上形成硅膜。 随后，通过等离子体氮化方法将硅膜完全氮化，由氮化硅膜代替。 随后，通过等离子体氧化方法氧化氮化硅膜的表面层，以被上部氧化硅膜代替。 形成作为由下部氧化硅膜，氮化硅膜和上部氧化硅膜构成的多层绝缘膜的ONO膜。
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9.发明授权公开(公告)号：US06444539B1
公开(公告)日：2002-09-03
申请号：US09784892
申请日：2001-02-15
申请人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
发明人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
IPC分类号： H01L2176
CPC分类号： H01L21/7621 , H01L21/3085 , H01L21/3086 , H01L21/76232
摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.
摘要翻译： 一种用于产生浅沟槽隔离的半导体装置和方法。 该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。 间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。 多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域 。 随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。
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公开(公告)号：US20070262374A1
公开(公告)日：2007-11-15
申请号：US11878296
申请日：2007-07-23
申请人： Masahiko Higashi , Manabu Nakamura , Kentaro Sera , Hiroyuki Nansei , Yukihiro Utsuno , Hideo Takagi , Tatsuya Kajita
发明人： Masahiko Higashi , Manabu Nakamura , Kentaro Sera , Hiroyuki Nansei , Yukihiro Utsuno , Hideo Takagi , Tatsuya Kajita
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/0217 , H01L21/022 , H01L21/02252 , H01L21/28282 , H01L21/31155 , H01L21/3185 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/66833
摘要： After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.
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