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1.发明申请公开(公告)号：US20110125962A1
公开(公告)日：2011-05-26
申请号：US12919318
申请日：2009-02-26
申请人： Mitsuhiro Nimura , Tatsumi Sakamoto , Toyoji Hiyokawa , Hiroyoshi Masuda , Tomofumi Shibata , Kazuyuki Hirakawa , Atsushi Yamazaki , Masahiro Hyakusawa , Masahiro Takahashi
发明人： Mitsuhiro Nimura , Tatsumi Sakamoto , Toyoji Hiyokawa , Hiroyoshi Masuda , Tomofumi Shibata , Kazuyuki Hirakawa , Atsushi Yamazaki , Masahiro Hyakusawa , Masahiro Takahashi
IPC分类号： G06F12/08
CPC分类号： G01C21/32
摘要： A map updating system includes: an update processing unit for performing update processing by reading data required in the update processing from a cache area of a memory when the data are stored in the cache area and from a map database when the data are not stored in the cache area; a cache storage unit for storing the data read by the update processing unit in the cache area; a processing memory capacity determination unit for determining a processing memory capacity, which is a capacity of the memory required as an update processing area, on the basis of the content of map data to be subjected to the update processing; and a cache capacity determination unit for determining a cache capacity, which is a capacity of the memory allocated to the cache area, on the basis of the processing memory capacity.
摘要翻译： 地图更新系统包括：更新处理单元，用于当数据存储在高速缓存区域中时，从存储器的高速缓存区域读取更新处理中所需的数据，并且当数据未被存储在地图数据库中时，执行更新处理 缓存区; 高速缓存存储单元，用于将由更新处理单元读取的数据存储在高速缓存区域中; 处理存储器容量确定单元，用于基于要进行更新处理的地图数据的内容来确定作为更新处理区域所需的存储器的容量的处理存储器容量; 以及高速缓存容量确定单元，用于基于处理存储器容量确定作为分配给高速缓存区域的存储器的容量的高速缓存容量。
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2.发明授权公开(公告)号：US08769237B2
公开(公告)日：2014-07-01
申请号：US12919318
申请日：2009-02-26
申请人： Mitsuhiro Nimura , Tatsumi Sakamoto , Toyoji Hiyokawa , Hiroyoshi Masuda , Tomofumi Shibata , Kazuyuki Hirakawa , Atsushi Yamazaki , Masahiro Hyakusawa , Masahiro Takahashi
发明人： Mitsuhiro Nimura , Tatsumi Sakamoto , Toyoji Hiyokawa , Hiroyoshi Masuda , Tomofumi Shibata , Kazuyuki Hirakawa , Atsushi Yamazaki , Masahiro Hyakusawa , Masahiro Takahashi
IPC分类号： G06F13/00
CPC分类号： G01C21/32
摘要： A map updating system includes: an update processing unit for performing update processing by reading data required in the update processing from a cache area of a memory when the data are stored in the cache area and from a map database when the data are not stored in the cache area; a cache storage unit for storing the data read by the update processing unit in the cache area; a processing memory capacity determination unit for determining a processing memory capacity, which is a capacity of the memory required as an update processing area, on the basis of the content of map data to be subjected to the update processing; and a cache capacity determination unit for determining a cache capacity, which is a capacity of the memory allocated to the cache area, on the basis of the processing memory capacity.
摘要翻译： 地图更新系统包括：更新处理单元，用于当数据存储在高速缓存区域中时，从存储器的高速缓存区域读取更新处理中所需的数据，并且当数据未被存储在地图数据库中时，执行更新处理 缓存区; 高速缓存存储单元，用于将由更新处理单元读取的数据存储在高速缓存区域中; 处理存储器容量确定单元，用于基于要进行更新处理的地图数据的内容来确定作为更新处理区域所需的存储器的容量的处理存储器容量; 以及高速缓存容量确定单元，用于基于处理存储器容量确定作为分配给高速缓存区域的存储器的容量的高速缓存容量。
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公开(公告)号：US09911856B2
公开(公告)日：2018-03-06
申请号：US12900145
申请日：2010-10-07
IPC分类号： H01L29/786 , H01L29/423
CPC分类号： H01L29/7869 , H01L29/42384 , H01L29/78606 , H01L29/78696
摘要： One of objects is to provide a semiconductor device with stable electric characteristics, in which an oxide semiconductor is used. The semiconductor device includes a thin film transistor including an oxide semiconductor layer, and a silicon oxide layer over the thin film transistor. The thin film transistor includes a gate electrode layer, a gate insulating layer whose thickness is equal to or larger than 100 nm and equal to or smaller than 350 nm, the oxide semiconductor layer, a source electrode layer and a drain electrode layer. In the thin film transistor, the difference of the threshold voltage value is 1 V or less between before and after performance of a measurement in which the voltage of 30 V or −30 V is applied to the gate electrode layer at a temperature of 85° C. for 12 hours.
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公开(公告)号：US09635313B2
公开(公告)日：2017-04-25
申请号：US13538560
申请日：2012-06-29
CPC分类号： G06F3/04845 , G06F3/1454 , G06F17/30056 , G06F2203/04803 , G06F2203/04806 , G06Q10/10 , H04L12/1813 , H04L12/1822 , H04L12/1827 , H04L65/403 , H04M2250/62 , H04N7/15
摘要： An information processing system and a method for operating same are provided. The information processing system includes a first information processing apparatus and a second information processing apparatus. The first information processing apparatus is configured to display a first synchronous image in a first window, the first window having an operation right. The second information processing apparatus has a synchronous state or an asynchronous state. The second information processing apparatus is configured to: display a second synchronous image; in response to a first request, switch from the synchronous state to the asynchronous state; and in response to a second request, switch from the asynchronous state to the synchronous state.
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公开(公告)号：US09627198B2
公开(公告)日：2017-04-18
申请号：US12894791
申请日：2010-09-30
IPC分类号： H01L21/00 , H01L21/84 , H01L21/02 , H01L29/786 , H01L27/12
CPC分类号： H01L21/02554 , G02F1/1368 , G02F1/167 , H01L21/02164 , H01L21/02172 , H01L21/02266 , H01L21/02422 , H01L21/02565 , H01L21/02631 , H01L21/477 , H01L27/1225 , H01L27/127 , H01L27/3262 , H01L29/24 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor.
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6.发明授权Electronic device including memory arrays with variable resistance storage elements arranged on different sides of a word line driving unit 有权电子设备包括具有布置在字线驱动单元的不同侧上的可变电阻存储元件的存储器阵列公开(公告)号：US09535834B2
公开(公告)日：2017-01-03
申请号：US14563645
申请日：2014-12-08
申请人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
发明人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
IPC分类号： G06F12/08 , G11C13/00 , G11C11/4099 , G11C11/16
CPC分类号： G11C13/004 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0207 , G06F12/08 , G06F12/0875 , G06F2212/2024 , G06F2212/452 , G06F2212/60 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C2013/0054 , G11C2213/79 , G11C2213/82
摘要： An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.
摘要翻译： 电子设备包括半导体器件，其中半导体器件包括：用于驱动多个字线的字线驱动单元; 布置在字线驱动单元的一侧的第一单元阵列; 布置在所述字线驱动单元的另一侧的第二单元阵列; 布置在所述第一单元阵列和所述第二单元阵列之间的偏置电压产生单元，用于基于流过所述第一单元阵列中包括的所述第一参考电阻元件的电流和所述第二单元中包括的所述第二参考电阻元件来产生偏置电压 阵列 第一读取控制单元; 和第二读取控制单元。
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公开(公告)号：US09484091B2
公开(公告)日：2016-11-01
申请号：US14636740
申请日：2015-03-03
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
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8.发明授权Processing apparatus, system, method and program for processing information to be shared 有权用于处理要共享的信息的处理装置，系统，方法和程序公开(公告)号：US09398233B2
公开(公告)日：2016-07-19
申请号：US13880267
申请日：2012-07-10
CPC分类号： H04N5/265 , G06F19/00 , G06F19/321 , G16H80/00 , H04L12/1827 , H04M3/567 , H04N7/15
摘要： An information processing apparatus, an information processing system, and a method of processing information are provided. In one embodiment, the information processing apparatus includes a processor, and a memory device storing instructions. When executed by the processor, the instructions cause the processor to receive, from a first information processing apparatus, area specifying information and location information, the area specifying information specifying a display area in an image, the display area including a plurality of partial images, the location information indicating at least one location of the plurality of partial images. The instructions further cause the processor to transmit, to a second information processing apparatus, the area specifying information and the location information.
摘要翻译： 提供信息处理装置，信息处理系统和处理信息的方法。 在一个实施例中，信息处理设备包括处理器和存储指令的存储器件。 当处理器执行时，指令使得处理器从第一信息处理设备接收区域指定信息和位置信息，区域指定信息指定图像中的显示区域，显示区域包括多个部分图像， 所述位置信息指示所述多个部分图像中的至少一个位置。 所述指令还使所述处理器向所述第二信息处理设备发送所述区域指定信息和所述位置信息。
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公开(公告)号：US09308602B2
公开(公告)日：2016-04-12
申请号：US13333349
申请日：2011-12-21
申请人： Kazuhiro Hayashimoto , Yuta Fujinuma , Tsukasa Hagihara , Shuichi Usui , Yoshitaka Sanuki , Masahiro Takahashi
发明人： Kazuhiro Hayashimoto , Yuta Fujinuma , Tsukasa Hagihara , Shuichi Usui , Yoshitaka Sanuki , Masahiro Takahashi
CPC分类号： B23K26/28 , B23K26/082 , B23K26/244 , B23K26/32 , B23K26/322 , B23K2101/006 , B23K2101/18 , B23K2101/34 , B23K2103/04 , B23K2103/08 , B23K2103/50
摘要： A laser lap welding method by irradiating of a laser beam from one side of a plurality of overlapped workpieces (1, 2), the method includes the steps of: scanning (La) the laser beam in the forward direction along a predetermined section of the workpieces; reversing the scanning direction of the laser beam at a terminating end (t) of the predetermined section; scanning (Lb) the laser beam in the backward direction and terminating of the irradiating of the laser beam onto the predetermined section, wherein the scanning of the laser beam in the backward direction is offset from the scanning of the laser beam in the forward direction such that a part of weld bead (12) formed by the laser scanning in the backward direction overlaps the weld bead (11) formed by the laser scan in the forward direction.
摘要翻译： 一种通过从多个重叠工件（1,2）的一侧照射激光束的激光搭接焊接方法，所述方法包括以下步骤：沿着向前方向沿着预定部分扫描（La）激光束 工件 在所述预定部分的终止端（t）反转所述激光束的扫描方向; 沿着反方向扫描（Lb）激光束并终止将激光束照射到预定部分上，其中激光束沿向后方向的扫描偏离激光束在向前方向上的扫描，例如 通过沿向后方向的激光扫描形成的焊道（12）的一部分与沿着向前方向的激光扫描形成的焊道（11）重叠。
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公开(公告)号：US09136388B2
公开(公告)日：2015-09-15
申请号：US13549867
申请日：2012-07-16
IPC分类号： H01L29/26 , H01L29/786
CPC分类号： H01L29/7869 , H01L29/24 , H01L29/78618
摘要： Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.
摘要翻译： 提供了能够实现所谓的常关断开关元件的晶体管的结构及其制造方法。 提供了通过提高晶体管的特性实现高速响应和高速操作的半导体器件的结构及其制造方法。 提供了一种高度可靠的半导体器件。 在其中半导体层，源极和漏极电极层，栅极绝缘层和栅极电极层以该顺序堆叠的晶体管中。 作为半导体层，含有铟，镓，锌和氧中的至少四种元素的氧化物半导体层，铟的组成比（原子百分比）为镓和a的组成比的两倍以上 使用锌的组成比。
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