公开(公告)号：US06849555B2

公开(公告)日：2005-02-01

申请号：US10449522

申请日：2003-05-30

申请人： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

发明人： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

IPC分类号： C23C14/56 ,  C23C16/44 ,  H01L21/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/302 ,  H01L21/461 ,  H01L21/677 ,  H01L21/768

CPC分类号： H01L21/67167 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/67739 ,  H01L21/76882 ,  H01L21/76888 ,  Y10S438/974

摘要： An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

摘要翻译： 提供了可用于形成具有多层结构的金属布线层和使用其的晶片处理方法的集成的原位簇型晶片处理装置。 晶片处理装置包括可以排出并具有多个闸阀的传送室，多个真空处理室，每个真空处理室可以经由一个闸阀连接到传送室;以及负载锁定室，其可以 被排出并且可连接到用于将氧基气体进料到负载锁定室中的第一气体供给管线。 在晶片处理方法中，在一个真空处理室中的晶片上形成预定层。 晶片上的预定层在负载锁定室或氧气氛室中被氧化。

公开(公告)号：US06432820B1

公开(公告)日：2002-08-13

申请号：US09921165

申请日：2001-08-02

申请人： Myoung-bum Lee ,  Jong-myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

发明人： Myoung-bum Lee ,  Jong-myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76888 ,  H01L2221/1089

摘要： A method is provided for forming a metal wiring layer of a semiconductor device, which is performed in an airtight space, the pressure of which is maintained below atmospheric pressure, to form a metal deposition prevention layer. An interlayer dielectric layer pattern is formed on a semiconductor substrate so as to define a hole region. A metal film is formed on the top surface of the interlayer dielectric layer pattern under a vacuum state so as to expose the side walls of the hole region. The metal layer is oxidized in the airtight space, the pressure of which is maintained below atmospheric pressure in an oxygen atmosphere, thereby forming a metal deposition prevention layer. A metal liner is selectively formed at the side walls of the hole region. A metal layer is formed inside the hole region defined by the metal liner and on the metal deposition prevention layer. The metal liner is heat-treated and reflowed.

摘要翻译： 提供了一种用于形成半导体器件的金属布线层的方法，该方法是在压力保持在大气压以下的气密空间中进行，以形成金属沉积防止层。 在半导体衬底上形成层间绝缘层图案，以限定一个孔区。 在真空状态下在层间电介质层图案的顶表面上形成金属膜，以露出孔区域的侧壁。 金属层在气氛中被氧化，其压力在氧气氛中保持低于大气压，从而形成金属沉积防止层。 在孔区域的侧壁上选择性地形成金属衬垫。 在由金属衬垫和金属沉积防止层限定的孔区域内形成金属层。 金属衬垫被热处理和回流。

公开(公告)号：US06586340B2

公开(公告)日：2003-07-01

申请号：US10098029

申请日：2002-03-13

申请人： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

发明人： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

IPC分类号： H01L21302

CPC分类号： H01L21/67167 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/67739 ,  H01L21/76882 ,  H01L21/76888 ,  Y10S438/974

摘要： An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

公开(公告)号：US06955983B2

公开(公告)日：2005-10-18

申请号：US10373368

申请日：2003-02-24

申请人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

发明人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

摘要翻译： 半导体器件的金属互连通过在衬底上形成包括孔的电介质图案，并在孔的外部和电介质层图案上形成阻挡金属层来制造。 至少一些阻挡金属层被氧化。 在孔的氧化阻挡金属层上选择性地形成抗成核层，该氧化的阻挡金属层露出孔中的氧化的阻挡金属层。 然后在孔中的暴露的氧化阻挡层上选择性地形成金属层。

公开(公告)号：US06391769B1

公开(公告)日：2002-05-21

申请号：US09525154

申请日：2000-03-14

申请人： Jong-myeong Lee ,  Hyun-seok Lim ,  Byung-hee Kim ,  Gil-heyun Choi ,  Sang-in Lee

发明人： Jong-myeong Lee ,  Hyun-seok Lim ,  Byung-hee Kim ,  Gil-heyun Choi ,  Sang-in Lee

IPC分类号： H01L214763

CPC分类号： H01L21/76855 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76888 ,  H01L2221/1089

摘要： A method for forming a metal interconnection filling a contact hole or a groove having a high aspect ratio, and a contact structure fabricated thereby. An interdielectric layer pattern, having a recessed region serving as a contact hole, a via hole or a groove, is formed on a semiconductor substrate. A barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer. The anti-nucleation layer is formed by forming a metal layer overlying the barrier metal layer in regions other than the recessed region, and then spontaneously oxidizing the metal layer in a vacuum. Also, the anti-nucleation layer may be formed by in-situ forming the barrier metal layer and the metal layer and then oxidizing the metal layer by an annealing process. Subsequently, a metal plug is selectively formed in the recessed region, surrounded by the barrier metal layer, thereby forming a metal interconnection for completely filling the contact hole or the groove having a high aspect ratio. A metal liner may be formed instead of the metal plug, followed by forming a metal layer filling the region surrounded by the metal liner, thereby forming a metal interconnection for completely filling the contact hole or groove having a high aspect ratio.

摘要翻译： 一种用于形成填充高纵横比的接触孔或槽的金属互连的方法，以及由此制造的接触结构。 在半导体衬底上形成具有用作接触孔的凹陷区域，通孔或沟槽的电介质层图案。 在形成介电层图案的所得结构的整个表面上形成阻挡金属层。 仅在阻挡金属层的非凹陷区域选择性地形成抗成核层。 通过在除了凹陷区域之外的区域中形成覆盖阻挡金属层的金属层，然后在真空中自发氧化金属层，形成抗成核层。 此外，抗成核层可以通过原位形成阻挡金属层和金属层，然后通过退火处理来氧化金属层而形成。 随后，在由阻挡金属层包围的凹陷区域中选择性地形成金属插塞，从而形成用于完全填充接触孔或具有高纵横比的沟槽的金属互连。 可以形成金属衬垫而不是金属插塞，随后形成填充由金属衬垫包围的区域的金属层，从而形成用于完全填充具有高纵横比的接触孔或槽的金属互连。

公开(公告)号：US20050179141A1

公开(公告)日：2005-08-18

申请号：US11095006

申请日：2005-03-31

申请人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

发明人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

公开(公告)号：US07384866B2

公开(公告)日：2008-06-10

申请号：US11095006

申请日：2005-03-31

申请人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

发明人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

摘要翻译： 半导体器件的金属互连通过在衬底上形成包括孔的电介质图案，并在孔的外部和电介质层图案上形成阻挡金属层来制造。 至少一些阻挡金属层被氧化。 在孔的氧化阻挡金属层上选择性地形成抗成核层，该氧化的阻挡金属层露出孔中的氧化的阻挡金属层。 然后在孔中的暴露的氧化阻挡层上选择性地形成金属层。

公开(公告)号：US20110003476A1

公开(公告)日：2011-01-06

申请号：US12829776

申请日：2010-07-02

申请人： Jong-ho Yun ,  Gil-heyun Choi ,  Jong-myeong Lee

发明人： Jong-ho Yun ,  Gil-heyun Choi ,  Jong-myeong Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76895 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76879

摘要： A semiconductor device in which an increase of contact resistance Rc between a metal contact and a plug due to misalignment between the metal contact and the plug can be reduced and the difficulty of a Cu filling process during the process of forming the plug may be reduced. The semiconductor device includes a substrate including an active area and a device isolation layer; a metal contact that is formed on the substrate and is electrically connected to the active area; a landing pad formed on the metal contact by electroless plating; and a plug that is formed on the landing pad and is electrically connected to the metal contact via the landing pad.

摘要翻译： 可以减少由于金属接触和插塞之间的未对准而导致金属接触和插塞之间的接触电阻Rc增大的半导体器件，并且可以减少在形成插头的过程中Cu填充过程的困难。 半导体器件包括：衬底，其包括有源区和器件隔离层; 金属接触件，其形成在所述基板上并电连接到所述有源区域; 通过无电镀形成在金属接触件上的着陆垫; 以及形成在所述着陆板上并且经由所述着陆垫电连接到所述金属接触件的插头。

公开(公告)号：US07067417B2

公开(公告)日：2006-06-27

申请号：US10881642

申请日：2004-06-30

申请人： Hee-sook Park ,  Gil-heyun Choi ,  Jong-myeong Lee

发明人： Hee-sook Park ,  Gil-heyun Choi ,  Jong-myeong Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/02052 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76889 ,  H01L21/76897 ,  H01L27/10855 ,  Y10S438/906

摘要： A contact hole can be formed in an insulating layer to expose a surface of an underlying silicon layer at a bottom of the contact hole having a first size. A metal silicide layer can be formed beneath the bottom of the contact hole and removed to form a void beneath the contact hole having a second size that is greater than the first size.

摘要翻译： 可以在绝缘层中形成接触孔，以在具有第一尺寸的接触孔的底部露出下面的硅层的表面。 可以在接触孔的底部下方形成金属硅化物层，并移除以在接触孔下方形成具有大于第一尺寸的第二尺寸的空隙。

公开(公告)号：US08497207B2

公开(公告)日：2013-07-30

申请号：US12829776

申请日：2010-07-02

申请人： Jong-ho Yun ,  Gil-heyun Choi ,  Jong-myeong Lee

发明人： Jong-ho Yun ,  Gil-heyun Choi ,  Jong-myeong Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/76895 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76879

摘要： A semiconductor device in which an increase of contact resistance Rc between a metal contact and a plug due to misalignment between the metal contact and the plug can be reduced and the difficulty of a Cu filling process during the process of forming the plug may be reduced. The semiconductor device includes a substrate including an active area and a device isolation layer; a metal contact that is formed on the substrate and is electrically connected to the active area; a landing pad formed on the metal contact by electroless plating; and a plug that is formed on the landing pad and is electrically connected to the metal contact via the landing pad.

摘要翻译： 可以减少由于金属接触和插塞之间的未对准而导致金属接触和插塞之间的接触电阻Rc增大的半导体器件，并且可以减少在形成插头的过程中Cu填充过程的困难。 半导体器件包括：衬底，其包括有源区和器件隔离层; 金属接触件，其形成在所述基板上并电连接到所述有源区域; 通过无电镀形成在金属接触件上的着陆垫; 以及形成在所述着陆板上并且经由所述着陆垫电连接到所述金属接触件的插头。