公开(公告)号：US06586340B2

公开(公告)日：2003-07-01

申请号：US10098029

申请日：2002-03-13

申请人： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

发明人： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

IPC分类号： H01L21302

CPC分类号： H01L21/67167 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/67739 ,  H01L21/76882 ,  H01L21/76888 ,  Y10S438/974

摘要： An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

公开(公告)号：US06849555B2

公开(公告)日：2005-02-01

申请号：US10449522

申请日：2003-05-30

申请人： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

发明人： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

IPC分类号： C23C14/56 ,  C23C16/44 ,  H01L21/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/302 ,  H01L21/461 ,  H01L21/677 ,  H01L21/768

CPC分类号： H01L21/67167 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/67739 ,  H01L21/76882 ,  H01L21/76888 ,  Y10S438/974

摘要： An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

摘要翻译： 提供了可用于形成具有多层结构的金属布线层和使用其的晶片处理方法的集成的原位簇型晶片处理装置。 晶片处理装置包括可以排出并具有多个闸阀的传送室，多个真空处理室，每个真空处理室可以经由一个闸阀连接到传送室;以及负载锁定室，其可以 被排出并且可连接到用于将氧基气体进料到负载锁定室中的第一气体供给管线。 在晶片处理方法中，在一个真空处理室中的晶片上形成预定层。 晶片上的预定层在负载锁定室或氧气氛室中被氧化。

公开(公告)号：US06602782B2

公开(公告)日：2003-08-05

申请号：US09862937

申请日：2001-05-22

申请人： Myoung-bum Lee ,  Jong-Myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

发明人： Myoung-bum Lee ,  Jong-Myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76864 ,  H01L21/76876 ,  H01L21/76882 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a metal interconnects include forming an electrically insulating layer having a contact hole therein, on a substrate. A step is also performed to form an electrically conductive seed layer. The seed layer extends on a sidewall of the contact hole and on a portion of an upper surface of the electrically insulating layer extending adjacent the contact hole. The seed layer is sufficiently thick along an upper portion of the sidewall and sufficiently thin along a lower portion of the sidewall that an upper portion of the contact hole is partially constricted by the seed layer and a constricted contact hole is thereby defined. An anti-nucleation layer is deposited on a portion of the seed layer that extends outside the constricted contact hole. The constricted contact hole is used as a mask to inhibit deposition of the anti-nucleation layer adjacent a bottom of the constricted contact hole. A metal liner is then formed on a portion of the electrically conductive seed layer that defines a sidewall of the constricted contact hole. Next, a metal interconnect layer is reflowed into the constricted contact hole to thereby fill and bury the contact hole.

摘要翻译： 形成金属互连的方法包括在基板上形成其中具有接触孔的电绝缘层。 还进行步骤以形成导电种子层。 种子层在接触孔的侧壁上延伸，并且在邻近接触孔延伸的电绝缘层的上表面的一部分上延伸。 种子层沿着侧壁的上部足够厚，并且沿着侧壁的下部足够薄，接触孔的上部被种子层部分地收缩，从而限定了收缩的接触孔。 在种子层的在收缩的接触孔外延伸的部分上沉积抗成核层。 收缩的接触孔用作掩模以抑制邻接于缩小的接触孔的底部的防着色层的沉积。 然后在导电种子层的限定收缩的接触孔的侧壁的部分上形成金属衬垫。 接下来，将金属互连层回流到收缩的接触孔中，从而填充并埋入接触孔。

公开(公告)号：US06432820B1

公开(公告)日：2002-08-13

申请号：US09921165

申请日：2001-08-02

申请人： Myoung-bum Lee ,  Jong-myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

发明人： Myoung-bum Lee ,  Jong-myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76888 ,  H01L2221/1089

摘要： A method is provided for forming a metal wiring layer of a semiconductor device, which is performed in an airtight space, the pressure of which is maintained below atmospheric pressure, to form a metal deposition prevention layer. An interlayer dielectric layer pattern is formed on a semiconductor substrate so as to define a hole region. A metal film is formed on the top surface of the interlayer dielectric layer pattern under a vacuum state so as to expose the side walls of the hole region. The metal layer is oxidized in the airtight space, the pressure of which is maintained below atmospheric pressure in an oxygen atmosphere, thereby forming a metal deposition prevention layer. A metal liner is selectively formed at the side walls of the hole region. A metal layer is formed inside the hole region defined by the metal liner and on the metal deposition prevention layer. The metal liner is heat-treated and reflowed.

摘要翻译： 提供了一种用于形成半导体器件的金属布线层的方法，该方法是在压力保持在大气压以下的气密空间中进行，以形成金属沉积防止层。 在半导体衬底上形成层间绝缘层图案，以限定一个孔区。 在真空状态下在层间电介质层图案的顶表面上形成金属膜，以露出孔区域的侧壁。 金属层在气氛中被氧化，其压力在氧气氛中保持低于大气压，从而形成金属沉积防止层。 在孔区域的侧壁上选择性地形成金属衬垫。 在由金属衬垫和金属沉积防止层限定的孔区域内形成金属层。 金属衬垫被热处理和回流。

公开(公告)号：US07384866B2

公开(公告)日：2008-06-10

申请号：US11095006

申请日：2005-03-31

申请人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

发明人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

摘要翻译： 半导体器件的金属互连通过在衬底上形成包括孔的电介质图案，并在孔的外部和电介质层图案上形成阻挡金属层来制造。 至少一些阻挡金属层被氧化。 在孔的氧化阻挡金属层上选择性地形成抗成核层，该氧化的阻挡金属层露出孔中的氧化的阻挡金属层。 然后在孔中的暴露的氧化阻挡层上选择性地形成金属层。

公开(公告)号：US20050179141A1

公开(公告)日：2005-08-18

申请号：US11095006

申请日：2005-03-31

申请人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

发明人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

公开(公告)号：US06955983B2

公开(公告)日：2005-10-18

申请号：US10373368

申请日：2003-02-24

申请人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

发明人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

摘要翻译： 半导体器件的金属互连通过在衬底上形成包括孔的电介质图案，并在孔的外部和电介质层图案上形成阻挡金属层来制造。 至少一些阻挡金属层被氧化。 在孔的氧化阻挡金属层上选择性地形成抗成核层，该氧化的阻挡金属层露出孔中的氧化的阻挡金属层。 然后在孔中的暴露的氧化阻挡层上选择性地形成金属层。

公开(公告)号：US06391769B1

公开(公告)日：2002-05-21

申请号：US09525154

申请日：2000-03-14

申请人： Jong-myeong Lee ,  Hyun-seok Lim ,  Byung-hee Kim ,  Gil-heyun Choi ,  Sang-in Lee

发明人： Jong-myeong Lee ,  Hyun-seok Lim ,  Byung-hee Kim ,  Gil-heyun Choi ,  Sang-in Lee

IPC分类号： H01L214763

CPC分类号： H01L21/76855 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76888 ,  H01L2221/1089

摘要： A method for forming a metal interconnection filling a contact hole or a groove having a high aspect ratio, and a contact structure fabricated thereby. An interdielectric layer pattern, having a recessed region serving as a contact hole, a via hole or a groove, is formed on a semiconductor substrate. A barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer. The anti-nucleation layer is formed by forming a metal layer overlying the barrier metal layer in regions other than the recessed region, and then spontaneously oxidizing the metal layer in a vacuum. Also, the anti-nucleation layer may be formed by in-situ forming the barrier metal layer and the metal layer and then oxidizing the metal layer by an annealing process. Subsequently, a metal plug is selectively formed in the recessed region, surrounded by the barrier metal layer, thereby forming a metal interconnection for completely filling the contact hole or the groove having a high aspect ratio. A metal liner may be formed instead of the metal plug, followed by forming a metal layer filling the region surrounded by the metal liner, thereby forming a metal interconnection for completely filling the contact hole or groove having a high aspect ratio.

摘要翻译： 一种用于形成填充高纵横比的接触孔或槽的金属互连的方法，以及由此制造的接触结构。 在半导体衬底上形成具有用作接触孔的凹陷区域，通孔或沟槽的电介质层图案。 在形成介电层图案的所得结构的整个表面上形成阻挡金属层。 仅在阻挡金属层的非凹陷区域选择性地形成抗成核层。 通过在除了凹陷区域之外的区域中形成覆盖阻挡金属层的金属层，然后在真空中自发氧化金属层，形成抗成核层。 此外，抗成核层可以通过原位形成阻挡金属层和金属层，然后通过退火处理来氧化金属层而形成。 随后，在由阻挡金属层包围的凹陷区域中选择性地形成金属插塞，从而形成用于完全填充接触孔或具有高纵横比的沟槽的金属互连。 可以形成金属衬垫而不是金属插塞，随后形成填充由金属衬垫包围的区域的金属层，从而形成用于完全填充具有高纵横比的接触孔或槽的金属互连。

公开(公告)号：US06951814B2

公开(公告)日：2005-10-04

申请号：US10649154

申请日：2003-08-27

申请人： Byung-hee Kim ,  Gil-heyun Choi ,  Ju-young Yun ,  Jung-hun Seo

发明人： Byung-hee Kim ,  Gil-heyun Choi ,  Ju-young Yun ,  Jung-hun Seo

IPC分类号： H01L21/28 ,  B05D5/12 ,  C23C16/00 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/768

CPC分类号： H01L21/28556 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/7684 ,  H01L21/76877

摘要： Methods of forming a metal wiring layer on an integrated circuit include forming an insulating pattern including a recess region on an integrated circuit substrate. A metal layer is formed in the recess region and on a top surface of the insulting pattern. The metal layer is removed from the top surface of the insulating pattern adjacent the recess region and from an upper portion of the recess region. An aluminum film is formed on the metal layer at a process temperature less than a reflow temperature of the metal layer to substantially fill the upper portion of the recess region after removing the metal layer. A metal film is formed on the aluminum film at a process temperature less than the reflow temperature of the etched metal layer.

摘要翻译： 在集成电路上形成金属布线层的方法包括在集成电路基板上形成包括凹部区域的绝缘图案。 在凹陷区域和绝缘图案的顶表面上形成金属层。 金属层从绝缘图案的顶表面与凹陷区域相邻并且从凹陷区域的上部移除。 在金属层上以低于金属层的回流温度的工艺温度形成铝膜，以在去除金属层之后基本上填充凹部区域的上部。 在低于蚀刻金属层的回流温度的工艺温度下，在铝膜上形成金属膜。

公开(公告)号：US20130012023A1

公开(公告)日：2013-01-10

申请号：US13533653

申请日：2012-06-26

申请人： In-sun Park ,  Gil-heyun Choi ,  Ji-soon Park ,  Jong-myeong Lee ,  Jong-won Hong ,  Hei-seung Kim

发明人： In-sun Park ,  Gil-heyun Choi ,  Ji-soon Park ,  Jong-myeong Lee ,  Jong-won Hong ,  Hei-seung Kim

IPC分类号： H01L21/308

CPC分类号： H01L23/48 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76816 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/06 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

摘要翻译： 根据示例性实施例，形成微图案的方法包括在衬底的虚拟区域上形成具有第一宽度的虚拟图案，并且在衬底的有源线区域上形成具有第二宽度的单元图案。 有源线区域可以与虚拟区域相邻，并且第二宽度可以小于第一宽度。 该方法可以进一步包括通过在有源线区域和虚拟区域上形成种子层来形成镶嵌金属化，在基片的整个表面上形成导电材料层，并平坦化导电材料层以形成金属线。