公开(公告)号：US3663871A

公开(公告)日：1972-05-16

申请号：US3663871D

申请日：1970-02-16

Applicant: NIPPON ELECTRIC CO

Inventor： NAKANUMA SHO ,  TSUJIDE TOHRU ,  WADA TOSHIO

IPC: H01L21/283 ,  G11C16/04 ,  G11C17/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L29/00 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L11/14

CPC classification number: H01L29/792 ,  G11C16/04 ,  G11C16/0466 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/28167 ,  H01L21/31616 ,  H01L21/3162 ,  H01L29/00

Abstract: A metal-insulator-semiconductor (MIS) semiconductor read-only memory element employs, as the gate insulator film, an alumina film formed through a novel hydrolytic deposition process.

Abstract translation: 金属绝缘体半导体（MIS）半导体只读存储元件采用通过新的水解沉积工艺形成的氧化铝膜作为栅极绝缘膜。

公开(公告)号：US3702466A

公开(公告)日：1972-11-07

申请号：US3702466D

申请日：1970-11-04

Applicant: NIPPON ELECTRIC CO

Inventor： NAKAGIRI MASARU ,  ONODA KATSUHIRO ,  IGARASHI RYO ,  WADA TOSHIO ,  NAKANUMA SHO ,  TSUJIDE TOHRU

IPC: G11C16/04 ,  H01L29/792 ,  G11C11/40

CPC classification number: H01L29/792 ,  G11C16/0466

Abstract: A semiconductor integrated circuit includes a plurality of insulated gate field effect memory transistors arranged in a rowcolumn matrix. Each of the memory transistors has an insulating film for establishing electron tapping centers. The source areas of the memory transistors are in the form of teeth-like projections which extend into the space defined between similarly formed projections in the memory transistor drain areas.

Abstract translation: 半导体集成电路包括排列成行列矩阵的多个绝缘栅场效应存储晶体管。 每个存储晶体管具有用于建立电子攻丝中心的绝缘膜。 存储晶体管的源极区域呈齿形突起的形式，其延伸到在存储晶体管漏极区域中类似形成的突起之间限定的空间中。

公开(公告)号：US3688389A

公开(公告)日：1972-09-05

申请号：US3688389D

申请日：1970-02-19

Applicant: NIPPON ELECTRIC CO

Inventor： NAKANUMA SHO ,  TSUJIDE TOHRU ,  WADA TOSHIO

IPC: H01L29/78 ,  H01L21/00 ,  H01L29/00 ,  H01L29/76 ,  B01J17/00 ,  H01G13/00

CPC classification number: H01L29/00 ,  H01L21/00 ,  H01L29/76

Abstract: A method for fabricating an integrated gate field effect transistor is disclosed wherein an induced conduction region is formed between the source and drain regions by the application of a suitable potential between the gate electrode and substrate. The surface of the device is irradiated by a high-energy beam, thereby to form a narrow channel in the conduction region which defines the gate channel of the field effect transistor.

Abstract translation: 公开了一种用于制造集成栅极场效应晶体管的方法，其中通过在栅电极和衬底之间施加合适的电势，在源区和漏区之间形成感应导电区。 器件的表面被高能束照射，从而在限定场效应晶体管的栅极沟道的导电区域中形成窄通道。

公开(公告)号：US3665423A

公开(公告)日：1972-05-23

申请号：US3665423D

申请日：1970-03-13

Applicant: NIPPON ELECTRIC CO

Inventor： NAKANUMA SHO ,  TSUJIDE TOHRU ,  WADA TOSHIO ,  IGARASHI RYO ,  ONODA KATSUHIRO

IPC: H01L21/283 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC classification number: G11C16/0466 ,  H01L29/511 ,  H01L29/792

Abstract: A memory matrix device is disclosed in which an MIS semiconductor element is employed as the memory element. The semiconductor element has an insulating film disposed between the semiconductor substrate and conductor electrode. That film contains capture centers which capture electrons upon the application of a voltage exceeding a critical value across the electrode and substrate.

公开(公告)号：US3646527A

公开(公告)日：1972-02-29

申请号：US3646527D

申请日：1970-03-31

Applicant: NIPPON ELECTRIC CO

Inventor： WADA TOSHIO ,  ONODA KATSUHIRO ,  IGARASHI RYO ,  NAKANUMA SHO ,  TSUJIDE TOHRU

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/00 ,  H01L29/51 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L13/00

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L29/00 ,  H01L29/51

Abstract: Data is written into a memory storage device by applying a negative voltage to the gate electrode of an MIS-type transistor, and a positive voltage to at least one of the drain and source of that transistor. The voltage difference between the gate and the source or drain exceeds a critical voltage so that electrons are injected and trapped in the gate film. Also disclosed is a memory matrix in which a plurality of MIS transistors are arranged in a matrix array and have their gate and source-drain electrodes connected to row-and-column drive lines.